Abstract: The device is connected to a memory (7) by an address bus and a data bus. It is characterized in that, on a clock output, it delivers a clock signal (clki_b) to be sent to the clock input of the memory (6), in that the clock signal. (clki) utilized for buffering the addresses and the data to be sent to the memory is the same, with the possible exception of having undergone signal inversion, as the one (clki_b) delivered on the clock output, and in that the same signal (clki_b) is utilized by the buffer (r1) receiving the data from the memory to buffer the data sent by the dynamic memory on the data bus.

Abstract: The present invention has been made in consideration of thin devices efficiently communicating ideas and transactions into data networks by using other devices with fill functional user interface in the networks. According to one aspect of the present invention, the thin device exclusively controls the authentication of a rendezvous that is associated with a user account in a server. The thin device running a micro-browser provisions the rendezvous with a set of credential information in an authenticated and secure communication session so that the provisioning process is truly proprietary. To access the user account, the other devices equipped with well known browsers must submit the correct credential information to the rendezvous for verification in the server.

Abstract: Disclosed is a computer system for in-system reprogramming of a fixed flash ROM when access to the fixed flash ROM is not possible. The computer system includes a main board on which the fixed flash ROM is mounted; a fixed ROM socket for mounting on the fixed flash ROM; and a backup flash ROM for insertion in the flash ROM socket such that the backup flash ROM is connected to the fixed flash ROM. Further, the computer system is booted with an operating system stored in the backup flash ROM.

Abstract: A system and method for controlling the manufacture of semiconductor wafers using model predictive control is provided. In accordance with one embodiment, a tool output of the manufacturing tool is determined based on a first wafer run. Using the tool output, a tool input for a subsequent wafer run is determined by minimizing an optimization equation being dependent upon a model which relates tool output to tool process state and tool process state to tool input and previous tool process state. The tool input is then provided to the manufacturing tool for processing a second wafer run. In this manner, processing by the tool or tool age is taken into account in determining the tool input for a subsequent run. This can reduce variations in tool output from run-to-run and improve the characteristics of the ultimately formed semiconductor devices.

Abstract: An internal high voltage to be used in an output circuit is generated by a plurality of charge pumps according to an externally supplied clock signal, and commonly provided to output buffers of the output circuit. In a clock synchronous semiconductor device, chip occupation area as well as current dissipation can be decreased.

Abstract: A digital system includes a clock line carrying a clock signal and a communication bus with a signal time of flight longer than a cycle of the clock signal. A master device is connected to the communication bus and the clock line. The master device selectively applies signals to the communication bus. A set of slave devices are connected to the communication bus and the clock line. Each slave device of the set of slave devices has an associated latency delay arising from its position on the communication bus. Each slave device includes delay circuitry to compensate for the associated latency delay such that the master device observes a uniform minimum latency for each slave device in response to applying signals to the communication bus.

Abstract: The present invention provides an interface for exchanging clocking signals and other information between a computer subsystem based on a first clocking scheme of a first processor and a second processor. The second processor and computer subsystem are coupled to the interface. The interface may be included on a circuit card that is removably coupled to the computer subsystem. The interface includes an emulator for emulating the first clocking scheme thereby enabling the second processor to function with the computer subsystem.

Abstract: A host controller performs a centralized controlled over the operation of an information processing apparatus as a whole. Codes which are read out for booting the information processing apparatus are stored in a ROM in advance. The host controller copies the contents of the ROM into a high speed storage element and reads out the storage contents of the high speed storage element to boot the apparatus when a VCC power supply is turned on after the VCC power supply is once turned off. This allows the apparatus to be booted based on the contents read out from the high speed storage element which can be read much faster than the ROM.

Abstract: The communications interface enables a processor unit to dialog with an IC card having an elementary time unit (ETU) for transmitting one bit that is equal to (K/Fs). The IC card includes a microprocessor, a clock pin for application of an external clock signal enabling the microprocessor of the IC card to be clocked, and an I/O pin. The microprocessor receives external data or transmits data via the I/O pin. The communications interface includes a serial communications line for interchanging data with the IC card via the I/O pin. The communications interface also includes a transmitting module, which is written-addressable by the processor unit and includes a serialization module for serializing and transmitting, over the serial communications line, data received from the processor unit. The communications interface also includes a receiving module, which is read-addressable by the processor unit and includes a serialization module for serializing data received over the serial communications line.

Abstract: A monitor includes a file that identifies one or more compatible monitors and/or a list of features of the monitor. A processing unit, such as a computer, that does not specifically support the particular monitor may nonetheless configure itself to operate effectively with the monitor. If the processing unit supports a compatible monitor, it configures itself to operate with the compatible monitor. Otherwise, the processing unit may configure itself to support the features of the particular monitor.

Abstract: A method and system for quality-of-service in a data-over-cable system using configuration protocol messaging is provided. The method and system include determining whether a cable modem termination system has enough available bandwidth to provide a quality-of-service connection requested by a cable modem from a quality-of-service server. The quality-of-service server uses Dynamic Host Configuration Protocol (“DHCP”) messaging to send and receive quality-of-service identifiers indicating that the cable modem termination system has enough available bandwidth to provide a quality-of-service connection requested by a cable modem. The cable modem termination system creates a quality-of-service connection to a cable modem based on the quality-of-service identifiers returned from the quality-of-service server. The quality-of-service server using DHCP messaging provides a standard and efficient process to reserve bandwidth for quality-of-service connections in a data-over-cable system.

Abstract: Two instructions are provided to synchronize multiple processors (92) in a data processing system (80). A Transmit Sync instruction (TSYNC) transmits a synchronize processor interrupt (276) to all of the active processors (92) in the system (80). Processors (92) wait for receipt of the synchronize signal (278) by executing a Wait for Sync (WSYNC) instruction. Each of the processors waiting for such a signal (278) is activated at the next clock cycle after receipt of the interrupt signal (278). An optional timeout value is provided to protect against hanging a waiting processor (92) that misses the interrupt (278). Whenever the WSYNC instruction is activated by receipt of the interrupt (278), a trace is started to trace a fixed number of events to an internal Trace Cache (58).

Abstract: An information processing apparatus is constructed so that a frequency of an external clock to be supplied to a central processing unit (CPU) which includes a phase locked loop (PLL) circuit is gradually increased from a first frequency to a second frequency within a latency time required for the PLL circuit to make a phase lock, when an operation mode of the CPU is switched from a first mode to a second mode.

Abstract: A hold/reset mode selection counter includes a counter unit composed of a plurality of counter blocks to perform a counting operation, a mode selection unit that detects a count enable signal length, and a control unit that enables or disables the counter unit. A detection unit generates a signal that holds or pauses the counter unit. The hold/reset mode selection counter controls the counting operation and a reset operation so that the operations are performed only when necessary, and a number of the counter blocks can be reduced. Thus, the hold/reset mode selection counter does not unconditionally perform a counting operation in accordance with an enable signal or perform a circular counting operation.

Abstract: Improved approaches to providing thermal and power management for a computing device are disclosed. These approaches facilitate intelligent control of a processor's clock frequency and/or a fan's speed so as to provide thermal and/or power management for the computing device.

Abstract: A method and apparatus are provided for simultaneously characterizing the disturbance of a dynamical system and the dynamic response model of the system. The disturbance is characterized by a sum of reference signals weighted by disturbance parameters. The dynamic response model is similarly characterized by a set of response parameters, which model the relationship between a set of test signals and the response to these test signals. The disturbance parameters and the response parameters are estimated jointly to provide a characterization of the dynamical system.

Abstract: A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other clock rate. The first and second clock rates are in virtual synchronism and have a fixed ratio between them. The computer chip set utilizes a phase signal generator capable of generating a set of phase signals and a signal conversion logic circuit for generating the output signal referencing one of the first and second clock rates other than the one referenced by the input signal. This computer chip set can allow the computer mother board to be operated without waiting a state so that the data processing efficiency of the computer mother board can be enhanced.

Abstract: A method and apparatus for configuring an electronic device for operation according to one of a plurality of product variants. Upon initialization of the device for use, identifying data for the user of the device is entered into the device. The identifying data is used to determine a selected set of configuration data from one of a plurality of sets of configuration data that are stored in the device. The electronic device is then configured to operate according to a particular product variant defined by the selected set of configuration data.

Abstract: A method is used with a computer that is capable of searching for a first identifier. The first identifier is associated with a first loader that causes the computer to load a virtual mode operating system and not a real mode operating system. The method includes providing a second loader to load both the virtual mode operating system and the real mode operating system into a memory of the computer. A second identifier that is associated with the second loader is provided to identify the second loader as the first loader.

Abstract: An improved time transfer mechanism and method are disclosed. In one embodiment, the present invention provides a computer implemented method for transferring time, includes generating a first time stamp at a processor; triggering a time transfer event; generating a second time stamp at the processor; and receiving a reference time stamp at the processor. Triggering the time transfer event can further include sending a request for a time stamp signal to a device that is dedicated to time synchronization. The present invention also includes specific hardware for performing the time transfer method.