Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; a magnetic layer over the substrate; a magnetic tunnel junction (MTJ) cell over the magnetic layer; and a non-magnetic conductive layer between the magnetic layer and the MTJ cell. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.

Abstract: A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.

Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.

Abstract: A storage device includes a nonvolatile memory device having a plurality of memory cells and a storage controller. Each memory cell is set to one of a plurality of memory cell states, wherein distinct subsets of the memory cell states are associated with one of a plurality of data sets. The storage controller accesses data stored in one of the memory cells in a first state, performs a multiplier-accumulator (MAC) operation on the data, and sets the one memory cell to a second state corresponding to a result of the MAC operation to perform an in-place update.

Abstract: A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current in open blocks during read operations using read voltage ramp rate control. The controller determines whether a block is open or closed. If the block is closed, the controller causes a read voltage to be applied to one of the block's word lines at a first ramp rate. If the block is open, the controller causes a read voltage to be applied to another of the block's word lines at a slower, second ramp rate. The controller further causes a read voltage to be applied to another word line of the open block at a different, third ramp rate. Thus, read voltages for open blocks may ramp slower than read voltages for closed blocks, as well as ramp at different rates for different word lines in open blocks.

Abstract: A system-on-chip (SoC) includes a system memory, a memory controller, and a memory management system coupled therebetween. The memory management system is configured to receive, from the memory controller, a first control signal that is indicative of a memory operation associated with the system memory, and output and provide a second control signal to the system memory to control an execution of the memory operation. The second control signal is outputted such that when the memory operation corresponds to a first read operation, the first read operation is executed with the system memory, and when the memory operation corresponds to a first write operation, a second read operation is executed with the system memory followed by the first write operation. Thus, the memory management system prevents memory corruption of the system memory when an asynchronous reset event is detected in the SoC.

Abstract: An integrated memory device can include an array of memory cells with decoding and sensing circuitry, a memory controller, read and write circuitry associated to the sensing circuitry, logic circuit portions in the read and write circuitry including at least a logic element receiving a data stream on a data input and a clock signal on a clock input, and a programmable or trimmable delay element or circuit upstream to the data input or the clock input for self trimming the internal timing of said at least a logic element by aligning in time the clock signal and/or the data stream. Operating parameters of the integrated circuit can be set for self trimming an internal timing of the integrated circuit.

Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.

Abstract: A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory having a plurality of wordlines. The controller circuit is configured to program, with foggy-fine programming, a first portion of the plurality of wordlines to store first program data, program, with the foggy-fine programming, one or more wordlines of the plurality of wordlines in a non-fine state, the one or more wordlines neighboring the first portion, and program, with the foggy-fine programming, a second portion of the plurality of wordlines to store second program data, the second portion neighboring the one or more wordlines.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

Abstract: A memory controller for controlling an operation of a semiconductor memory device including a memory block including a plurality of sub-blocks. The memory controller includes a randomizer. The randomizer includes: seed table storage configured to store a plurality of seed tables respectively corresponding to the plurality of sub-blocks, and to generate a seed, based on sub-block information of received original data; a random sequence generator configured to generate a random sequence, based on the seed generated by the seed table storage; and an operating component configured to generate random data, based on the random sequence and the original data.

Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

Abstract: Disclosed herein is an apparatus that includes a memory cell array, a plurality of TSVs penetrating a semiconductor chip, an output circuit configured to output a data to the TSVs, an input circuit configured to receive a data from the TSVs, a pad supplied with a data from outside, and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.

Abstract: This application provides a data writing method and a storage device. The method is applied to a solid-state storage device SSD, and the method includes: receiving a write command, where the write command carries a type of to-be-written data; determining, based on the type of to-be-written data, a type of storage area that is in an SSD and into which the to-be-written data is written, where the SSD includes a plurality of types of storage areas; determining, based on the type of storage area, a target storage area into which the to-be-written data is written; and writing the to-be-written data into the target storage area. In embodiments of this application, data processing efficiency can be improved.

Abstract: A method of manufacturing an array of magnetic random access memory cells includes writing to a magnetic random access memory cell. The writing to a memory cell includes determining an optimum write current for the array of memory cells, and applying the optimum write current to a first memory cell in the array. A first read current is applied to the first memory cell to determine whether a magnetic orientation of the first memory cell has changed in response to applying the optimum write current. A second write current is applied to the first memory cell when the magnetic orientation of the first memory cell has not changed. The second write current is different from the optimum write current. A second read current is applied to the first memory cell to determine whether the magnetic orientation of the first memory cell changed in response to applying the second write current.