Abstract: Provided herein may be a storage device and a method of operating the storage device. A memory device may include a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform an operation on memory cells selected from among the plurality of memory cells, a voltage variation detector configured to generate voltage variation information indicating whether a voltage variation has occurred in a supply voltage during performance of the operation, a power register configured to store the voltage variation information, a status register configured to store status information indicating an operating status of the memory device, and a register output controller configured to update the status information provided from the status register based on the voltage variation information.

Abstract: A method includes performing a quantity of write cycles on memory components. The method can further include monitoring codewords, and, for each of the codewords including a first error parameter value, determining a second error parameter value. The method can further include determining a probability that each of the codewords is associated with a particular one of the second error parameter values at the first error parameter value and determining a quantity of each of the codewords that are associated with each of the determined probabilities. The method can further include determining a statistical boundary of the quantity of each of the codewords and determining a correlation between the quantity of write cycles performed and the corresponding determined statistical boundary of the quantity of each of the codewords.

Abstract: A memory device includes logic to detect the last page written in multi-plane non-volatile memory. The device includes a memory array, and a storage controller. The memory array includes multiple planes and multiple word lines operable on the memory array. The storage controller is configured to divide the word lines into contiguous sub-ranges and assign a subset of the word lines to boundaries of the sub-ranges. Each word line of the subset of word lines is assigned to a page in a different one of the memory planes. The controller operates the subset of word lines to sense a page programmed or erased state from each of the memory planes in parallel.

Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a CAM block configured to store CAM data required for various operations, a page buffer group configured to store the CAM data read from the CAM block through a CAM read operation, an extra register configured to store extra data generated by performing an operation on the CAM data, an operation logic configured to perform an operation of checking a defect in the extra register, registers configured to sequentially store operation data generated through the defect check operation, a fixed register configured to store fixed data obtained through an operation performed to check an error in the CAM data, and core circuits configured to perform the CAM read operation and transmit the operation data and the CAM data to the extra register, the registers, and the fixed register.

Abstract: Methods, systems, and devices related to domain-based access in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory array may be organized according to domains, which may refer to various configurations or collections of access lines, and selections thereof, of different portions of the memory array. In various examples, a memory device may determine a plurality of domains for a received access command, or an order for accessing a plurality of domains for a received access command, or combinations thereof, based on an availability of the signal development cache.

Abstract: A memory sub-system configured to adaptively and/or iteratively determine sub-operations of executing a read command to retrieve data from memory cells. For example, after receiving the read command from a processing device of a memory sub-system, a memory device starts an atomic operation of executing the read command in the memory device. The memory device can have one or more groups of memory cells formed on an integrated circuit die and a calibration circuit configured to measure signal and noise characteristics of memory cells in the memory device. During the atomic operation, the calibration circuit generates outputs, based on which a read manager of the memory sub-system identifies sub-operations to be performed in the atomic operation and/or decides to end the atomic operation.

Abstract: Techniques are described for maintaining a stable voltage difference in a memory device, for example, during a critical operation (e.g., a sense operation). The voltage difference to be maintained may be a read voltage across a memory cell or a difference associated with a reference voltage, among other examples. A component (e.g., a local capacitor) may be coupled, before the operation, with a node biased to a first voltage (e.g., a global reference voltage) to sample a voltage difference between the first voltage and a second voltage while the circuitry is relatively quiet (e.g., not noisy). The component may be decoupled from the node before the operation such that a node of the component (e.g., a capacitor) may be allowed to float during the operation. The voltage difference across the component may remain stable during variations in the second voltage and may provide a stable voltage difference during the operation.

Abstract: A memory management operation is executed on a plurality of memory dies of a memory sub-system. The memory sub-system determines whether a first measured current level corresponding to execution of the memory management operation satisfies a condition pertaining to a threshold peak current level. The memory sub-system determines whether a second measured current level corresponding to execution of the memory management operation satisfies the condition pertaining to the threshold peak current level. Mask data is generated identifying the first measured current level and the second measured current level. A request is received from a host system to execute the memory management operation. The memory sub-system performs, based on the mask data, a peak current management action during execution of the memory management operation.

Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

Abstract: A memory device includes a plurality of sub-word line drivers with, each sub-word line driver configured to receive a main word line signal and configured to drive a respective local word line to at least one of an active state, a soft-landing state, an off state based on the main word line signal and a phase signal. The memory device also includes a plurality of phase drivers with each phase driver configured to generate the respective phase signal. The memory device can further include a processing device configured to drive the respective local word line to the soft-landing state prior to entering the off state when transitioning from the active state to the off state so as to provide row hammer stress mitigation between adjacent local word lines corresponding to the plurality of sub-word line drivers. Each sub-word line driver includes a diode-connected transistor.

Abstract: A storage device includes a memory device including a plurality of memory cells respectively storing data having a plurality of bits, and a memory controller including an operation block including a plurality of unit circuits executing a predetermined function, and a core block executing a control operation on the plurality of memory cells in response to a command from a host. The core block selects at least portions of the plurality of unit circuits to determine selection unit circuits, and generates a control command specifying an operation order of the selection unit circuits. In the operation block, the selection unit circuits operate by the operation order to determine a control voltage required for the control operation, and store the control voltage in at least one of the memory controller or the memory device.

Abstract: Provided are devices and methods relating to temperature control in a solid state drive (SSD). A SSD (10, 110, 210, 310, 410, 510, 610, 710) including a housing (12, 112, 212, 312, 412, 512, 612, 712) including a plurality of sides surrounding an interior region. The SSD (10, 110, 210, 310, 410, 510, 610, 710) includes at least one vent (14, 114, 214, 314, 414, 514, 614, 714) on the housing (12, 112, 212, 312, 412, 512, 612, 712), the at least one vent (14, 114, 214, 314, 414, 514, 614, 714) configured to be opened and closed in response to a signal.

Abstract: A programmable and reprogrammable processor on a control semiconductor die is disclosed. The processor controls various operations on a memory semiconductor die to which it is bonded, such as read, write, and erase. The processor issues control signals to operate circuits such as voltage regulators, sense amplifiers, and data latches. Because the processor is reprogrammable, it is possible to modify the operation of the circuits. For example, the processor can execute updated instructions to control the voltage regulators to modify the timing and/or magnitude of voltages applied to control lines in the memory semiconductor die. In one aspect, a page mapping scheme is updated in order to more evenly distribute a bit error rate (BER) across the pages. In one aspect, a read equalization scheme is updated. In one aspect, a technique for reading soft bits is updated.

Abstract: A memory system performs analog sanitization of memory using a partial programming operation to overwrite existing data taking into account the relative voltage levels in the memory cells. By taking into account the relative voltage levels, the timing of a partial programming operation can be controlled to provide matched voltage levels in the memory cells so that conventional computer forensic techniques for data recovery are ineffective.

Abstract: According to one embodiment, a memory system includes a memory controller configured to send a first command set including arithmetic operation target data and an address that designates a memory cell to store weight data; and a nonvolatile semiconductor memory configured to receive the first command set from the memory controller, read the weight data from the memory cell designated by the address, perform an arithmetic operation based on the arithmetic operation target data and the weight data, and send arithmetic operation result data to the memory controller.

Abstract: A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.

Abstract: The present technology relates to a storage device and a method of operating the same. The storage device includes a memory controller configured to generate and output a get parameter command set, including normal addresses and a dummy address, during a parameter read operation, and a memory device configured to, in response to the get parameter command set, read parameter data that is stored in a CAM block and store the read parameter data in target registers corresponding to the normal addresses. The memory device stores dummy data in a dummy register corresponding to the dummy address.

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

Abstract: A novel memory device is provided. The memory device including a plurality of memory cells arranged in a matrix, and each of the memory cells includes a transistor and a capacitor. The transistor includes a first gate and a second gate, which include a region where they overlap with each other with a semiconductor layer therebetween. The memory device has a function of operating in a “writing mode”, a “reading mode”, a “refresh mode”, and an “NV mode”. In the “refresh mode”, data retained in the memory cell is read, and then the read data is written to the memory cell again for first time. In the “NV mode”, data retained in the memory cell is read, the read data is written to the memory cell again for second time, and then a potential at which the transistor is turned off is supplied to the second gate. The “NV mode” operation enables data to be stored for a long time even when power supply to the memory cell is stopped. The memory cell can store multilevel data.

Abstract: Data reading method, device, and storage medium of a non-volatile memory are provided. The method includes obtaining address information and decoding the address information to determine an address of a corresponding memory cell; when the address of the memory cell is in a selected region, adjusting a first determination reference value to obtain a second determination reference value; applying a readout current to the memory cell, and obtaining a determination current outputted by the memory cell; and comparing a value range of the determination current outputted by the memory cell with the second determination reference value and reading out data content stored in the memory cell.