Patents Examined by Thuan Do
  • Patent number: 9391467
    Abstract: In one embodiment, a battery charger can include: (i) a step-up converter configured to generate an output signal by boosting a DC input voltage, where a threshold voltage is greater than the DC input voltage; (ii) a charging control circuit configured to receive the output signal from the step-up converter, and to control charging of a battery; (iii) the charging control circuit being configured to regulate the output signal to maintain a charging current for the battery charging as a trickle current when a battery voltage is less than the threshold voltage; and (iv) the charging control circuit being configured to charge the battery directly by the output signal when the battery voltage is greater than the threshold voltage.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: July 12, 2016
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Chen Zhao, Shuai Cheng, Jie Yao
  • Patent number: 9390219
    Abstract: A method of detecting one or more faults in a semiconductor device that includes generating a first test pattern set from a primary node list and a fault list. The primary node list includes one or more nodes and the fault list identifies one or more faults. The method also includes generating one or more secondary node lists from the primary node list and generating a second test pattern set from at least the first test pattern set and the secondary node list. Each node of the one or more nodes of the primary node list is associated with a corresponding secondary node list of the one or more secondary node lists.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: July 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Sandeep Kumar Goel, Yuan-Han Lee
  • Patent number: 9381821
    Abstract: One aspect provides an apparatus configured to receive wireless charging power and wired charging power. The apparatus includes a first rectifier configured to receive wired charging power and to provide a first rectified output. The apparatus further includes a second rectifier configured to receive wireless charging power and to provide a second rectified output. The apparatus further includes a power-factor correction (PFC) module configured to receive the first and second rectified outputs, and further configured to provide a power-factor corrected output. The apparatus further includes an isolated DC-DC converter configured to receive the power-factor corrected output and to provide an isolated DC output. The apparatus further includes and a battery configured to receive the isolated DC output.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: July 5, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Nicholas Athol Keeling, Michael Le Gallais Kissin, Jonathan Beaver, Chang-Yu Huang
  • Patent number: 9378316
    Abstract: Design and verification support related to integrated circuits that includes acquiring a first use case diagram representing a function of an object subject to design and verification and an activity diagram representing a processing procedure of the object; analyzing a structure of the activity diagram acquired at the acquiring step; converting the activity diagram to a second use case diagram representing a function of the object, based on the structure analyzed at the analyzing; verifying uniformity of the first use case diagram and the second use case diagram; and outputting a verification result obtained at the verifying uniformity.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: June 28, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Ryosuke Oishi, Akio Matsuda
  • Patent number: 9373974
    Abstract: A portable device recharging system includes a base unit generating an electromagnetic field. A portable device includes a rechargeable battery inductively charged by the electromagnetic field. Spacers are disposed between the portable device and the base unit. The spacers support the portable device and maintain an air gap between the base unit and the portable device.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: June 21, 2016
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Shailendra Kaushik, Taeyoung Han, Dan Lascu, Jerome M. Stolicki, Xianxi Jin, Bahram Khalighi
  • Patent number: 9372951
    Abstract: Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Wang, Wei-Cheng Wu, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 9373969
    Abstract: Described is an energy share pack comprising a housing, at least one energy storage component within the housing, at least one energy conversion component within the housing, and a connection point for connecting to more than one of energy users, energy sources and other energy share packs simultaneously for sharing energy. The energy share pack may have an energy generation component for generating harvestable energy, and two or more ports of any combination of the following types: bidirectional power port, bidirectional USB port, unidirectional output power port, and unidirectional input power port. The share pack ports may operate simultaneously at different voltage levels, and at least one port may be bi-directional. Furthermore, the share packs may have an integrated display for providing information on the energy share pack in which the display is integrated and information about other energy share packs connected thereto.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: June 21, 2016
    Assignee: Revision Military S.a.r.l.
    Inventors: Steve Carkner, Len Donais, Eric Lanoue
  • Patent number: 9360863
    Abstract: Various embodiments for determining parameters for wafer inspection and/or metrology are provided.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: June 7, 2016
    Assignee: KLA-Tencor Corp.
    Inventors: Govind Thattaisundaram, Mohan Mahadevan, Ajay Gupta, Chien-Huei Adam Chen, Ashok Kulkarni, Jason Kirkwood, Kenong Wu, Songnian Rong
  • Patent number: 9355199
    Abstract: A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logic cells to make it difficult for reverse engineering programs to be used to discover the circuit's function.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: May 31, 2016
    Inventors: Lap Wai Chow, James P. Baukus, Bryan J. Wang, Ronald P. Cocchi
  • Patent number: 9352661
    Abstract: A power receiver is configured to supply current to a load and to be wirelessly operatively coupled to a power transmitter and includes a plurality of inductive elements. The power receiver further includes a circuit operatively coupled to the plurality of inductive elements and configured to be selectively switched among a plurality of coupling states. The circuit is further configured to be selectively switched such that each inductive element has a reactance state of a plurality of reactance states. The power receiver further includes a controller configured to select the coupling state and to select the reactance state of each inductive element based on one or more signals indicative of one or more operating parameters of at least one of the power receiver and the power transmitter.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: May 31, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Nicholas Athol Keeling, Chang-Yu Huang, Mickel Budhia, Michael Kissin, Jonathan Beaver
  • Patent number: 9350181
    Abstract: An efficient electronic cigarette charging device and a method for efficiently charging an electronic cigarette are provided, the device comprises an electronic cigarette case and a battery rod, the battery rod includes a charging management unit and an electronic cigarette battery unit, the electronic cigarette case includes an electronic cigarette case battery unit, a current sample unit, a micro-control unit and a adjustable voltage output unit, the current sample unit is configured to sample actual charging current the charging management unit to the electronic cigarette battery, and the micro-control unit is configured to compare the actual charging current with default battery constant charging current, and further control the adjustable voltage output unit to adjust the charging voltage output.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: May 24, 2016
    Assignee: HUIZHOU KIMREE TECHNOLOGY CO., LTD. SHENZHEN BRANCH
    Inventor: Zhiyong Xiang
  • Patent number: 9343918
    Abstract: According to an example embodiment, a balancing apparatus includes: bi-directional switches that are respectively connected to cells that are connected in series, a controller configured to measure voltages of the cells, and a multiwinding transformed connected to the bi-directional switches. The bi-directional switches are configured to control a flow of an electric current bi-directionally. The controller is configured to select a number of the cells for balancing based on the measured voltages of the cells. The controller is configured to turn on and turn off the bi-directional switches that are connected to selected cells based on the measured voltages. The multi-winding transformer is configured to transfer energy between the cells when the bi-directional switches connected to the selected cells are turned on.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 17, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-jung Yun, Tae-jung Yeo, Jang-pyo Park
  • Patent number: 9343922
    Abstract: A wireless energy transfer enabled battery includes a resonator that is positioned asymmetrically in a battery sized enclosure such that when two wirelessly enabled batteries are placed in close proximity the resonators of the two batteries have low coupling.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: May 17, 2016
    Assignee: WiTricity Corporation
    Inventors: Alexander Patrick McCauley, Morris P. Kesler, Volkan Efe, Katherine L. Hall
  • Patent number: 9342638
    Abstract: An improved approach is provided to implement performance checking. A check is performed as to whether two designs are equivalent without needing to analyze their outputs on a cycle-by-cycle basis, where the two designs are checked to see if they are equivalent on the transaction-level. Thereafter, the outputs for the transactions are analyzed relative to delay time periods, which allows verification and identification of possible performance issues and differences between the two designs.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: May 17, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Antonio Celso Caldeira, Jr., Rajeev Kumar Ranjan, Marcus Vinicius da Mata Gomes
  • Patent number: 9312690
    Abstract: A protective circuit is provided. The protective circuit includes a charging unit, a voltage regulating unit, and a comparing unit. The charging unit receives a rise signal and an over-current signal, and outputs a first reference voltage. The voltage regulating unit receives the first reference voltage and adjusts an output voltage according, to the first reference voltage and a feedback voltage. The comparing unit receives the feedback voltage and compares the feedback voltage with a first threshold voltage to determine whether to output the rise signal to the charging unit.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: April 12, 2016
    Assignee: ASMEDIA TECHNOLOGY INC.
    Inventor: Ting-Wen Su
  • Patent number: 9313878
    Abstract: A method for mitigating voltage stress on a PCB includes applying AC voltage to a multi-terminal condenser structure of a multi-layered PCB. The terminal condenser structure is formed by overlapping a plurality of conductive traces between board layers of the multi-layered PCB. A corresponding dielectric layer is disposed between the overlapping conductive traces of the board layers. The overlapping conductive traces include a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal and the third terminal are disposed on a first layer of the multi-layered PCB, and the second terminal and the fourth terminal are disposed on a bottom layer of the multi-layered PCB. The first terminal and the second terminal are connected to a ground point, and the third terminal and the fourth terminal are connected to the AC voltage. Voltage stresses on the PCB are mitigated utilizing the multi-terminal condenser structure.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 12, 2016
    Assignee: DOBLE ENGINEERING COMPANY
    Inventor: Robert Clark Woodward, Jr.
  • Patent number: 9306410
    Abstract: A wireless energy transfer enabled battery includes a resonator that is positioned asymmetrically in a battery sized enclosure such that when two wirelessly enabled batteries are placed in close proximity the resonators of the two batteries have low coupling.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: April 5, 2016
    Assignee: WiTricity Corporation
    Inventors: Alexander Patrick McCauley, Morris P. Kesler, Volkan Efe, Katherine L. Hall
  • Patent number: 9305125
    Abstract: An EDA tool for validating predefined timing paths having corresponding timing constraints in an integrated circuit (IC) design has a processor that performs a static-timing-analysis (STA) of the IC design and generates a STA report that includes the first set of timing constraints, which include a first number of clock cycles required for propagating the first multi-cycle timing path. A simulation-based checker based on a STA that counts a second number of clock cycles that is actually required by the first multi-cycle timing path to propagate is generated while performing a unit-delay, gate-level netlist simulation of the first-multiple cycle timing path. The first set of timing constraints then are modified so that the first multi-cycle timing path is redefined to require the second number of clock cycles to propagate.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: April 5, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Vipin Pandey, Sidhartha Taneja
  • Patent number: 9305701
    Abstract: Apparatus comprises: an induction, coil (40) arrangement, the induction coil arrangement having a first set of at least one coil (41) with a first diameter and a second set of at least one coil (42) with a second diameter, the second diameter being different to the first diameter, a first tap (A) connected at a first end of the first set, a second tap (B) connected at connection common to a second end of the first set and a first end of the second set, and a third tap (C) connected at a second end of the second set; a power transmit arrangement (61) selectively connectable to a first combination of two of the first to third taps; and a power receive arrangement (62) selectively connectable to a second combination of two of the first to third taps, the second combination being different to the first combination.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: April 5, 2016
    Assignee: Nokia Technologies Oy
    Inventors: Petri Vuori, Frank Borngräber
  • Patent number: 9298875
    Abstract: A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: March 29, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shaojie Xu, Yukit Tang, Pao-Po Hou, Derek C. Tao, Annie-Li-Keow Lum