Patents Examined by Thuan Do
  • Patent number: 9501603
    Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Harry Barowski, Joachim Keinert, Sridhar H. Rangarajan, Haoxing Ren, Sourav Saha
  • Patent number: 9501590
    Abstract: A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan chain in two different directions such that a fault may be resolved back to a specific region of the IC.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: November 22, 2016
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Paul A. Cunningham, Steev Wilcox, Vivek Chickermane
  • Patent number: 9495506
    Abstract: Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: November 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Hsin Chen, Kai-Ming Liu
  • Patent number: 9483594
    Abstract: This application discloses an electronic design automation tool configured to perform one or more static reset checks on reset functionality in a circuit design. The electronic design automation tool can detect the reset functionality in the circuit design, identify a portion of the circuit design having a set of resettable components, and determine whether the portion of the circuit design includes a reset design error based, at least in part, on the reset functionality in the circuit design. The static reset checks can include a domain congruency check, a reset skew check, and a glitch detection check, each of which can identify different design errors that may cause reset functionality in the circuit design to operate improperly.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: November 1, 2016
    Assignee: Mentor Graphics Corporation
    Inventors: Ka-kei Kwok, Ping Yeung, Priya Viswanathan
  • Patent number: 9478541
    Abstract: A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes reducing a fin pitch and a gate pitch of the vertical devices on the die. The method also includes scaling a wavelength to define at least one reduced area geometric pattern of the circuit layout.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: October 25, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Stanley Seungchul Song, Kern Rim, Jeffrey Junhao Xu, Matthew Michael Nowak, Choh Fei Yeap, Roawen Chen
  • Patent number: 9465896
    Abstract: A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan chain in two different directions such that a fault may be resolved back to a specific region of the IC.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 11, 2016
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Paul A. Cunningham, Steev Wilcox, Vivek Chickermane
  • Patent number: 9457680
    Abstract: There is provided a system and a computer-implemented method for storing electrical charge in an electric vehicle connected to a charging station. The method includes: attaining a minimum State of Charge (SOC) for the electric vehicle; determining a time to charge the electric vehicle to a maximum SOC; maintaining an electric vehicle SOC by repeatedly charging and allowing discharge of the electric vehicle between the minimum SOC and a threshold; and charging the electric vehicle to the maximum SOC when the determined time to charge the electric vehicle to a maximum SOC has elapsed, wherein the threshold is greater than the minimum SOC and the maximum SOC is greater than or equal to the threshold.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: October 4, 2016
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Satoru Shinzaki, Toshiharu Kumagai
  • Patent number: 9460261
    Abstract: A computer-implemented verification system for performing a system level or a system on chip level functional verification of integrated circuit is provided. The computer-implemented system includes one or more processors and a memory storing instructions defined by one or more modules of including a scenario compiler, a verification component and a software library component. The scenario compiler receives a set of verification scenario intents including at least one of test-application intents, constraints, device-programming intents and scenario-control intents. The scenario compiler generates one or more open verification methodology (OVM) and/or universal verification methodology (UVM) compliant test bench sequences and one or more scenario software implementations based on the set of verification scenario intents. The verification component interacts with the integrated circuit using the OVM and/or UVM compliant test bench sequences.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 4, 2016
    Inventors: Srivatsan Raghavan, Karthick Gururaj, Sandeep Pendharkar, Someshwar DK, Shrinivas Nagaraddi
  • Patent number: 9454637
    Abstract: A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws (KVL), and power conservation for the original circuit. A reporting tool shows the validation results and may be customized by the user. The tool can show in the original circuitry where the estimated results may be inaccurate.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 27, 2016
    Assignee: Worldwide Pro Ltd.
    Inventor: William Wai Yan Ho
  • Patent number: 9449127
    Abstract: An EDA tool for verifying timing constraints of an integrated circuit (IC) design includes a processor and a memory that stores register transfer level (RTL) code of the IC design and a timing constraint file. The processor generates a netlist based on the RTL code, and identifies asynchronous clock paths, false paths and multi-cycle paths in the netlist using the timing constraint file. The processor then inserts buffer cells for logic cells in the netlist. The processor also inserts buffer cells in the asynchronous clock paths, false paths, and multi-cycle paths. The processor delay annotates logic cells and clock delay cells with a zero delay value and the buffer cells with known delay values. The processor generates a modeled standard delay format (SDF) file and performs a gate level simulation (GLS) using the modeled SDF file.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: September 20, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Ateet Mishra, Shiva Belwal, Deepak Mahajan
  • Patent number: 9450274
    Abstract: A method and apparatus of creating a dynamically reconfigurable energy source comprised of individual, isolated, controllable energy modules, supported by software to measure and manage the energy modules and facilitate the reconfiguration, where the platform consisting of hardware, based upon an inverted H-Bridge circuitry, in combination with software which allows for real-time management, control, and configuration of the modules and uses a combination of software algorithms and localized electronic switches, to achieve a performance and functionality of the invention matching, or exceeding, traditional large, heavy, and expensive power electronics-based products used for charging, energy storage management, power inverting, and motor or load control.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: September 20, 2016
    Inventors: Tom V. Vo, Courtney A. Gras, Kent Kristensen, Sam Mahmodicherati
  • Patent number: 9450806
    Abstract: A method for expressing a hierarchy of scalabilities in complex systems, including a discrete event simulation and an analytic model, for analysis and prediction of the performance of multi-chip, multi-core, multi-threaded computer processors is provided. Further provided is a capacity planning tool for migrating data center systems from a source configuration which may include source systems with multithreaded, multicore, multichip central processing units to a destination configuration which may include destination systems with multithreaded, multicore and multichip central processing units, wherein the destination systems may be different than the source systems. Apparatus and methods are taught for the assembling of and utilization of linear and exponential scalability factors in the capacity planning tool when a plurality of active processor threads populate processors with multiple chips, multiple cores per chip and multiple threads per core.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: September 20, 2016
    Assignee: CA, Inc.
    Inventors: Kenneth C. Zink, Douglas M. Neuse, Christopher B. Walton
  • Patent number: 9438064
    Abstract: Systems, methods, and apparatuses for receiving charging power wirelessly are described herein. One implementation may include an apparatus for receiving charging power wirelessly from a charging transmitter having a transmit coil. The apparatus comprises a receiver communication circuit, coupled to a receive coil and to a load. The receiver communication circuit is configured to receive information associated with at least one characteristic of the charging transmitter. The apparatus further comprises a sensor circuit configured to measure a value of a short circuit current or an open circuit voltage associated with the receive coil. The apparatus further comprises a controller configured to compare the value of the short circuit current or the open circuit voltage to a threshold charging parameter set at a level that provides charging power sufficient to charge the load.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: September 6, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Nicholas Athol Keeling, Michael Le Gallais Kissin, Chang-Yu Huang, Jonathan Beaver, Mickel Bipin Budhia
  • Patent number: 9425639
    Abstract: A charging device for a rechargeable energy store which has a first induction coil includes: a coupling surface for positioning the first energy store; a second induction coil for generating a magnetic field in the area of the coupling surface to transfer electrical energy between the first and second induction coils; and a direction control system for bringing an alignment of the field of the second induction coil in line with an alignment of the first induction coil.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: August 23, 2016
    Assignee: Robert Bosch GmbH
    Inventor: Alexander Osswald
  • Patent number: 9423439
    Abstract: An apparatus and method for detecting a foreign object in a wireless power transmitting system are provided. In a case in which a foreign object is not detected prior to charging, an attempt to detect a foreign object detection during charging is performed, and when a foreign object is not detected while a power signal is being received, power is limited based on a temperature sensor.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 23, 2016
    Assignee: HANRIM POSTECH CO., LTD.
    Inventors: Chun Kil Jung, Byong Uk Hwang
  • Patent number: 9419452
    Abstract: The present invention provides an apparatus that includes a resistive control block (RCB) coupled to data lines of a universal serial bus (USB) connector charging port and is configured to change a level of resistance between the data lines. The apparatus further includes a sensing and adjustment block (SAB) that is configured to sense a predetermined level of overheating of the USB connector charging port and cause the RCB to increase the level of resistance resulting in the USB connector charging port to appear as a different type of port. In another embodiment, an apparatus includes a RCB and SAB. The RCB is coupled to an identification and ground lines of a USB connector and configured to change a level of resistance between them. The SAB is configured to sense a predetermine level of overheating of a USB connector and cause the RCB to decrease the level of resistance.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: August 16, 2016
    Assignee: Nokia Technologies Oy
    Inventors: Timo Juhani Toivanen, Jarmo Ilkka Saari, Pekka Eerikki Leinonen, Pasi Markus Koskinen
  • Patent number: 9411926
    Abstract: A method of generating, based on a first netlist of an integrated circuit, a second netlist includes generating layout geometry parameters for at least a portion of the first netlist of the integrated circuit, the portion including a first device. A third netlist is generated based on the first netlist and the layout geometry parameters. A description in the third netlist for modeling the first device is decomposed into a description in a fourth netlist for modeling a plurality of secondary devices. The second netlist is generated based on the fourth netlist.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: August 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui Yu Lee, Feng Wei Kuo, Jui-Feng Kuan, Simon Yi-Hung Chen
  • Patent number: 9411369
    Abstract: Docking stations that may facilitate the sharing or transfer of power among a portable computing device, a docking station, and an accessory. One example may provide power from an accessory to a portable computing device. Switches may be used to avoid harm from inadvertent contact with voltages on exposed terminals. Another example may provide power directly from a battery on a portable computing device to an accessory. Another may limit this direct connection to a first type of accessory. Examples may limit a power connection to another type of accessory through a regulator. Another example may power one or more internal circuits either through a portable computing device or an accessory, depending on a mode of operation of the portable computing device.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: August 9, 2016
    Assignee: Apple Inc.
    Inventors: Gerhard A. Schneider, Scott Krueger, Robert D. Watson
  • Patent number: 9400312
    Abstract: A battery system comprises at least two modules which include a plurality of battery cells, with each module being associated with a cell voltage detection unit which is connected to a central controller via a common communication bus. Each module additionally includes a module voltage detection unit which is connected to the central controller and is configured to separately detect the voltage of the associated module.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: July 26, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Andreas Bosch, Joachim Fetzer, Stefan Butzmann, Holger Fink, Martin Lang
  • Patent number: 9397506
    Abstract: An apparatus is provided that includes a first terminal to couple to a first node of a stacked battery pack having a first cell block and a second cell block, a second terminal to couple to a second node between the first cell block and the second cell block, and a voltage management circuit to detect an output voltage at the second terminal and to adjust energy within the battery pack based on the output voltage to be detected at the second terminal.
    Type: Grant
    Filed: October 1, 2011
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventor: Andy Keates