Patents Examined by Tian-Pong Chang
  • Patent number: 10133663
    Abstract: Data is stored on a non-volatile storage media in a sequential, log-based format. The formatted data defines an ordered sequence of storage operations performed on the non-volatile storage media. A storage layer maintains volatile metadata, which may include a forward index associating logical identifiers with respective physical storage units on the non-volatile storage media. The volatile metadata may be reconstructed from the ordered sequence of storage operations. Persistent notes may be used to maintain consistency between the volatile metadata and the contents of the non-volatile storage media. Persistent notes may identify data that does not need to be retained on the non-volatile storage media and/or is no longer valid.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: November 20, 2018
    Assignee: Longitude Enterprise Flash S.A.R.L.
    Inventors: David Atkisson, David Nellans, David Flynn, Jens Axboe, Michael Zappe
  • Patent number: 10133298
    Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: November 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Jin Cho, Jae-Geun Park, Young-Kwang Yoo, Soon-Suk Hwang
  • Patent number: 10133486
    Abstract: Methods, systems, and devices are described for displaying information on a visual display of a data storage device. The device may be an internal data storage device and may display information associated with various operation parameters or states of the data storage device. The data storage device may display, on the visual display, an indication that a data storage medium of the data storage device has been securely erased. The data storage medium may be securely erased by erasing an encryption key used to encrypt data stored on the data storage medium. The visual display may be electronic paper, mechanical, or chemical such that the information is displayed without power being applied to the data storage device.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: November 20, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Aliasghar Riahi, Mike H. Miller
  • Patent number: 10120801
    Abstract: Method and system are provided for object caching with mobility management for mobile data communication. The method may include: intercepting and snooping data communications at a base station between a user equipment and a content server without terminating communications; implementing object caching at the base station using snooped data communications; implementing object caching at an object cache server in the network, wherein the object cache server proxies communications to the content server from the user equipment; and maintaining synchrony between an object cache at the base station and an object cache at the object cache server.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Oliver M. Deakin, Victor S. Moore, Robert B. Nicholson, Colin J. Thorne
  • Patent number: 10114587
    Abstract: A memory device may include one or more multi-channel memories and an interface unit suitable for interfacing the multi-channel memories. The interface unit may include a first data interface suitable for transferring data for the first channel of the multi-channel memories, a second data interface suitable for transferring data for the second channel of the multi-channel memories, and an extra data interface suitable for transferring data for a selected one of the first channel and the second channel so that the data is additionally transmitted.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: October 30, 2018
    Assignee: SK Hynix Inc.
    Inventors: Young-Ook Song, Ki-Joong Kim, Jung-Hyun Kwon, Yong-Ju Kim
  • Patent number: 10108538
    Abstract: Methods, systems, and apparatus, including an apparatus for accessing data. In some implementations, an apparatus includes address offset value elements that are each configured to store an address offset value. For each address offset value element, the apparatus can include address computation elements that each store a value used to determine the address offset value. One or more processors are configured to receive a program for performing computations using tensor elements of a tensor. The processor(s) can identify, in the program, a prologue or epilogue loop having a corresponding data array for storing values of the prologue or epilogue loop and populate, for a first address offset value element that corresponds to the prologue or epilogue loop, the address computation elements for the first address offset value element with respective values based at least on a number of iterations of the prologue or epilogue loop.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: October 23, 2018
    Assignee: Google LLC
    Inventors: Olivier Temam, Harshit Khaitan, Ravi Narayanaswami, Dong Hyuk Woo
  • Patent number: 10055136
    Abstract: Systems and methods for maintaining guest input/output (I/O) tables in a swappable memory. An example method comprises: allocating, by a hypervisor running on a host computer system, one or more memory pages mapped into a memory space of a virtual machine running on the host computer system, to store a guest input/output (I/O) table comprising a plurality of I/O table entries, wherein each I/O table entry maps a device identifier of an I/O device to a memory address of a memory buffer associated with the I/O device; determining, by a processing device of the host computer system, that a memory page comprises one or more I/O table entries that reference memory buffers that are marked as being not accessible by associated I/O devices; and swapping out the memory page to a backing storage.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: August 21, 2018
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Andrea Arcangeli
  • Patent number: 10025633
    Abstract: The invention relates in particular to optimizing memory access in a microprocessor including several logic cores upon the resumption of executing a main application, and enabling the simultaneous execution of at least two processes in an environment including a hierarchically organized shared memory including a top portion and a bottom portion, a datum being copied from the bottom portion to the top portion for processing by the application. The computer is adapted to interrupt the execution of the main application. Upon an interruption in the execution of said application, a reference to a datum stored in a top portion of the memory is stored, wherein said datum must be used in order to enable the execution of the application. After programming a resumption of the execution of the application and before the resumption thereof, said datum is accessed in a bottom portion of the memory in accordance with the reference to be stored in a top portion of the memory.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: July 17, 2018
    Assignee: BULL SAS
    Inventors: Philippe Couvee, Yann Kalemkarian, Benoit Welterlen
  • Patent number: 10019376
    Abstract: A memory system includes a memory device including first and second storage regions, each comprising a plurality of memory blocks and a controller suitable for selecting a first mode or a second mode based on a method for accessing data stored in the memory device and mapping a logical address of the data into a physical address of the first storage region in the first mode and into a physical address of the second storage region in the second mode.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: July 10, 2018
    Assignee: SK Hynix Inc.
    Inventor: Ambrose Gihan de Silva
  • Patent number: 10019159
    Abstract: Systems, methods and devices for management of instances of virtual memory components for storing computer readable information for use by at least one first computing device, the system comprising at least one physical computing device, each physical computing device being communicatively coupled over a network and comprising: a physical memory component, a computing processor component, an operating system, a virtual machine monitor, and virtual memory storage appliances; at least one of the virtual memory storage appliances being configured to (a) accept memory instructions from the at least one first computing device, (b) instantiate instances of at least one virtual memory component, (c) allocate memory resources from at least one physical memory component for use by any one of the least one virtual memory components, optionally according to a pre-defined policy; and (d) implement memory instructions on the at least one physical memory component.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 10, 2018
    Assignee: Open Invention Network LLC
    Inventors: Jacob Taylor Wires, Andrew Warfield, Daniel Stodden, Dutch Meyer, Jean Maurice Guy Guyader, Keir Fraser, Timothy John Deegan, Brendan Anthony Cully, Christopher Clark, Mohammad Abdul-Amir
  • Patent number: 10002000
    Abstract: The disclosed embodiments provide a system that manages the use of a virtual disk. During operation, the system obtains trace data associated with a startup process that reads blocks from the virtual disk. Next, the system physically rearranges the blocks based on the trace data to increase the speed of the startup process. During execution of the startup process, the system also determines a progress of the startup process and uses the progress and the trace data to prefetch blocks from the virtual disk for use by the startup process.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: June 19, 2018
    Assignee: Open Invention Network, LLC
    Inventors: John Whaley, Thomas Joseph Purtell, II
  • Patent number: 10002092
    Abstract: An arithmetic processing unit including a memory controller configured to make variable-length access requests allowing a plurality of lengths to a memory, the memory controller comprising: a plurality of buffers configured to hold the access requests for each of the lengths of the access requests; and an arbitrator configured to select one of access requests stored in the plurality of buffers in accordance with a number of remaining resources of the memory.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: June 19, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Yuta Toyoda, Koji Hosoe, Akio Tokoyoda, Masatoshi Aihara, Makoto Suga
  • Patent number: 9990293
    Abstract: Techniques described herein generally include methods and systems related to improving energy efficiency in a chip multiprocessor by reducing the energy consumption of a DRAM cache for such a multi-chip processor. Methods of varying refresh interval may be used to improve the energy efficiency of such a DRAM cache. Specifically, a per-set refresh interval based on retention time of memory blocks in the set may be determined, and, starting from the leakiest memory block, memory blocks stored in the DRAM cache that are associated with data also stored in a lower level of cache are not refreshed.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: June 5, 2018
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9965383
    Abstract: A technique uses file system indirection to manage solid state devices (SSDs). Based on relocation of data on the SSDs from a first SSD storage block to a second SSD storage block, a flash translation layer (FTL) driver may update a per-volume indirection file to reference the second SSD storage block and no longer reference the first SSD storage block. Based on a mismatch between the per-volume indirection file and a buffer tree, the buffer tree is updated to reference the second SSD storage block. Alternatively, the FTL driver may create and insert an entry into a mapping table, wherein the entry may reference the first SSD storage block and also reference the second SSD storage block. The buffer tree may then be updated to reference the second SSD storage block based on the new entry, and the new entry may then be deleted after the buffer tree is updated.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: May 8, 2018
    Assignee: NetApp, Inc.
    Inventor: Indranil Bhattacharya
  • Patent number: 9948587
    Abstract: A method for data deduplication during execution of an application on a plurality of computing nodes, including: generating, by a first processor in a first computing node executing the application, a first message to process application data owned by a second computing node executing the application; receiving, by a first network interface (NI) of the first computing node, the first message; extracting, by the first NI, a first key from the first message; determining, by the first NI, the first key is not a duplicate; and placing, by the first NI and in response to the first key not being a duplicate, the first message on a network connecting the first computing node to the second computing node.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: April 17, 2018
    Assignee: Oracle International Corporation
    Inventors: Herbert Dewitt Schwetman, Jr., Pranay Koka, Arslan Zulfiqar
  • Patent number: 9921973
    Abstract: In one embodiment, a cache manager releases a list lock during a scan when a track has been identified as a track for cache removal processing such as demoting the track, for example. By releasing the list lock, other processors have access to the list while the identified track is processed for cache removal. In one aspect, the position of the previous entry in the list may be stored in a cursor or pointer so that the pointer value points to the prior entry in the list. Once the cache removal processing of the identified track is completed, the list lock may be reacquired and the scan may be resumed at the list entry identified by the pointer. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: March 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Benhase, Lokesh M. Gupta
  • Patent number: 9916260
    Abstract: A memory manager in a computer system that ages memory for high performance. The efficiency of operation of the computer system can be improved by dynamically setting an aging schedule based on a predicted time for trimming pages from a working set. An aging schedule that generates aging information that better discriminates among pages in a working set based on activity level enables selection of pages to trim that are less likely to be accessed following trimming. As a result of being able to identify and trim less active pages, inefficiencies arising from restoring trimmed pages to the working set are avoided.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: March 13, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Landy Wang
  • Patent number: 9891838
    Abstract: A method of operating a memory system including a nonvolatile memory, having a meta data region and a user data region, and a memory controller having a meta data manager. The method includes programming data to a memory block of the user data region and, by operation of the meta data manager, generating a meta log based on the programming. The meta log is stored to the memory controller. Upon a power-off operation, selectively storing the meta log to the meta data region of the nonvolatile memory based on status information of the nonvolatile memory.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: February 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jae Woo, Sungyong Seo, Otae Bae, Hyun-Seung Jei
  • Patent number: 9886376
    Abstract: An example method for host virtual address reservation comprises: reserving a host virtual address range within a virtual address space of a computer system; associating a first virtual memory device with a first guest physical address range a virtual machine running on the computer system; associating a second virtual memory device with a second guest physical address range of the virtual machine; mapping a first guest physical address of the first guest physical address range to a first host virtual address of the host virtual address range, wherein the first host virtual address is identified by an offset with respect to the first guest physical address; mapping a second guest physical address of the second guest physical address range to a second host virtual address of the host virtual address range, wherein the second host virtual address is identified by the offset with respect to the second guest physical address.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: February 6, 2018
    Assignee: Red Hat Israel, Ltd.
    Inventors: Paolo Bonzini, Michael Tsirkin
  • Patent number: 9886195
    Abstract: The disclosed embodiments provide a system for analyzing data from a monitored system. During operation, the system identifies a difference between a performance of an application and a service-level agreement (SLA) of the application. Next, the system determines a correlation between the performance of the application and a disk input/output (I/O) performance of a data storage device used by the application. When the correlation exceeds a threshold, the system outputs a recommendation to migrate the application between the data storage device and a different type of data storage device.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: February 6, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Zhenyun Zhuang, Sergiy Zhuk, Haricharan K. Ramachandra, Badrinath K. Sridharan