Patents Examined by Tifney Skyles
  • Patent number: 9754953
    Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, John K. Zahurak
  • Patent number: 9659994
    Abstract: An imaging device includes: a photoelectric conversion region that generates photovoltaic power for each pixel depending on irradiation light; and a first element isolation region that is provided between adjacent photoelectric conversion regions in a state of surrounding the photoelectric conversion region.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: May 23, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Tsutomu Imoto, Keiji Mabuchi
  • Patent number: 9647188
    Abstract: In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical traces thereon.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 9, 2017
    Assignee: COOLEDGE LIGHTING INC.
    Inventor: Michael A. Tischler
  • Patent number: 9640546
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: May 2, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
  • Patent number: 9634072
    Abstract: An organic light-emitting display device includes: a substrate; an active layer on the substrate; a gate electrode insulated from the active layer and overlapping with the active layer; a source electrode including a first source electrode layer, connected to the active layer, and a second source electrode layer connected to the first source electrode layer, the second source electrode layer being larger than the first source electrode layer; a drain electrode including a first drain electrode layer connected to the active layer, and a second drain electrode layer connected to the first drain electrode layer, the second drain electrode layer being larger than the first drain electrode layer; a first electrode directly connected to a top surface of the source electrode or the drain electrode; an intermediate layer on the first electrode and including an organic emission layer; and a second electrode on the intermediate layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 25, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chun-Gi You, Joon-Hoo Choi
  • Patent number: 9633962
    Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Ekta Misra, Christopher D. Muzzy, Wolfgang Sauter
  • Patent number: 9620462
    Abstract: A first cavity-down ball grid array (BGA) package includes a substrate member and an array of bond balls. The array of bond balls includes a pair of parallel extending rows of outer mesh bond balls and a row of inner signal bond balls that is parallel to the pair of rows of outer mesh bond balls. A surface-mount blocking element is disposed between the row of inner signal bond balls and the pair of rows of outer mesh bond balls. The surface-mount blocking element is either a passive or an active component of the BGA package. In one example, the first cavity-down BGA package is surface-mounted to a second cavity-down BGA package to form a package-on-package (POP) security module. The surface-mount blocking element provides additional physical barrier against the probing of the inner signal bond balls. Sensitive data is therefore protected from unauthorized access.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 11, 2017
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Ruben C. Zeta, Edgardo L. Chua Ching Chua
  • Patent number: 9614065
    Abstract: A power semiconductor device includes a power transistor including a plurality of transistor cells on a semiconductor die. At least some of the transistor cells are inhomogeneous by design so that the number of current filaments in the transistor cells with reduced local current density increases and fewer transient avalanche oscillations occur in the power transistor during operation.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: April 4, 2017
    Assignee: Infineon Technologies AG
    Inventor: Tao Hong
  • Patent number: 9601496
    Abstract: In a method of fabricating a semiconductor device, sacrificial layer patterns are formed by leaving portions of sacrificial layers, instead of completely removing the sacrificial layers. Thus, the reliability of the semiconductor device may be increased, and the process of manufacturing the same may be simplified.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: March 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanghoon Lee, Hyunyong Go, Sunggil Kim, Kyong-Won An, Woosung Lee, Yongseok Cho
  • Patent number: 9601619
    Abstract: An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A silicon germanium region is disposed in the opening, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
  • Patent number: 9601564
    Abstract: An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: March 21, 2017
    Assignee: NXP USA, INC.
    Inventors: Xu Cheng, Daniel J. Blomberg, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 9590058
    Abstract: A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 7, 2017
    Assignee: NXP USA, INC.
    Inventors: Cheong Min Hong, Sung-Taeg Kang
  • Patent number: 9577031
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate; and a plurality of convex structures formed on a surface of the substrate and arranged in a longitudinal direction of the substrate, each convex structure having a top surface, a bottom surface located on the surface of the substrate, a first end surface and a second end surface parallel to each other, and a front side surface and a rear side surface parallel to each other, in which the rear side surface of one of two adjacent convex structures and the front side surface of the other are located on a same plane to allow the plurality of convex structures to form a zigzag structure.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: February 21, 2017
    Inventors: Yuan Li, Lei Guo
  • Patent number: 9567460
    Abstract: Polymer compositions are described that are well suited for producing reflectors for light-emitting devices, such as light-emitting diodes. In one particular embodiment, the polymer composition contains a polymer resin, a white pigment, a silicone compound, and a nucleating agent. The polymer resin may comprise, for instance, a poly(1,4-cyclohexanedimethanol terephthalate). In accordance with the present disclosure, the composition also contains at least one silicone compound and at least one nucleating agent. The silicone compound and nucleating agent have been found to improve the molding processability and reflectance stability of the polymer composition.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: February 14, 2017
    Assignee: Ticona LLC
    Inventor: Bing Lu
  • Patent number: 9559044
    Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Hsien-Ming Tu, Chang-Pin Huang, Yu-Chia Lai, Tung-Liang Shao
  • Patent number: 9548336
    Abstract: Image sensors, and electronic devices including the same, include a first photo-sensing device sensing light in a full visible to near infrared ray region, a second photo-sensing device sensing light in a blue wavelength region, a third photo-sensing device sensing light in a red wavelength region, and a fourth photo-sensing device sensing light in a green wavelength region. At least one of the first photo-sensing device, the second photo-sensing device, the third photo-sensing device, and the fourth photo-sensing device includes a pair of light-transmitting electrodes facing each other, and a photoactive layer between the light-transmitting electrodes. The photoactive layer includes an organic light-absorbing material.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: January 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu Sik Kim, Satoh Ryuichi, Hong-Seok Lee
  • Patent number: 9508640
    Abstract: A method for forming a device with a multi-tiered contact structure includes forming first contacts in via holes down to a first level, forming a dielectric capping layer over exposed portions of the first contacts and forming a dielectric layer over the capping layer. Via holes are opened in the dielectric layer down to the capping layer. Holes are opened in the capping layer through the via holes to expose the first contacts. Contact connectors and second contacts are formed in the via holes such that the first and second contacts are connected through the capping layer by the contact connectors to form multi-tiered contacts.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 29, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Cheng-Wei Cheng, Szu-Lin Cheng, Keith E. Fogel, Edward W. Kiewra, Amlan Majumdar, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9503080
    Abstract: A radio-frequency (RF) switch circuit is configured to maintain a disconnection or a connection between a node and an antenna terminal. The RF switch circuit comprises one or more switch cells. A switch cell comprises one or more transistors. The switch cell comprises one or more gate-drain capacitors. The switch cell comprises one or more source-drain capacitors. A gate-drain capacitor is coupled between a gate of a transistor and a drain of the transistor. A source-drain capacitor is coupled between a source of a transistor and a drain of the transistor.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Jun-De Jin
  • Patent number: 9466742
    Abstract: A photoelectric conversion material is disclosed in the present invention and comprises at least a cone material. The cone material is composed of an isomer and comprises a plurality of grains. The sizes of the grains are arranged from smaller ones to larger ones along a direction. In the meantime, a method for fabricating the above photoelectric conversion material is also disclosed here. The method comprises the following steps. First, a precursor is provided. The precursor comprises at least a cone material and the cone material is a multilayer structured material, such as sodium titanate and potassium titanate, formed by stacking first materials and second materials. And then, the precursor is annealed to let the second materials leave from the cone material, and the cone material becomes the above photoelectric conversion material with a plurality of grains.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 11, 2016
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chi-Young Lee, Hsin-Tien Chiu, Po-Chin Chen, Min-Chiao Tsai
  • Patent number: 9438972
    Abstract: The present invention relates to a silicon based MEMS microphone, comprising a silicon substrate and an acoustic sensing part supported on the silicon substrate, wherein a mesh-structured back hole is formed in the substrate and aligned with the acoustic sensing part, the mesh-structured back hole includes a plurality of mesh beams which are interconnected with each other and supported on the side wall of the mesh-structure back hole, the plurality of mesh beams and the side wall define a plurality of mesh holes which all have a tapered profile and merge into one hole in the vicinity of the acoustic sensing part at the top side of the silicon substrate. The mesh-structured back hole can help to streamline the air pressure pulse caused, for example, in a drop test and thus reduce the impact on the acoustic sensing part of the microphone, and also serve as a protection filter to prevent alien substances such as particles entering the microphone.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: September 6, 2016
    Assignee: GOERTEK INC.
    Inventors: Zhe Wang, Mengjin Cai