Abstract: A frequency divider apparatus is a closed loop system of a recirculating memory element, at least one feedback memory element and an end memory element in series combination. Each memory element accepts a common clock. An end memory element output is logically combined with at least one of the other memory element outputs and provides an input to the closed loop system to generate a self-initializing state machine.

Abstract: An FPGA having a programmable frequency output is provided that achieves a (theoretical) M-times reduction in output jitter from a conventional direct digital synthesis (DDS) circuit, by running M accumulator circuits in parallel and combining the outputs in a time-staggered way. I Initially the frequency number N added into the accumulators is varied slightly for each accumulator by multiplying by a number, such as X/16 where X varies from 1 to 16 for each of 16 accumulator circuits. The accumulator circuits are further reconfigured so that the output of a register from a first accumulator provides feedback to the adder input in all of the accumulator circuits. The number of overflowing accumulator registers in a clock cycle will then indicate granularity spatially. To translate spatial granularity to time, a programmable delay circuit is connected to the output of each accumulator register.

Abstract: A voltage reference generating method, source, memory device and substrate containing the same include a voltage reference generator comprised of a bandgap voltage reference circuit including a first complementary-to-absolute-temperature (CTAT) signal and a second complementary-to-absolute-temperature (CTAT) signal. The voltage reference generator further includes a differential sensing device for generating a reference signal substantially insensitive to temperature variations over an operating temperature range by differentially sensing the first and second CTAT signals. The method includes generating first and second complementary-to-absolute-temperature (CTAT) signals and generating a reference signal that is substantially insensitive to temperature variations over an operating temperature range.

Abstract: A frequency programmable feed forward oscillator and triangular wave generator is disclosed having a first input for receiving an input voltage and a second input for receiving an input current. Circuitry within the device responsive to the input voltage scales the amplitude of a triangle wave form according to the provided input voltage and provides the scaled output voltage at a first output. In conjunction, the circuitry also generates a scaled PWM frequency responsive to the provided input current and provides this at a second output.

Abstract: A voltage source converter with a line-side diode rectifier, a load-side inverter with an electronic circuit, a power supply for the electronic circuit, and a slim DC link with a DC link capacitor is described. The slim DC link connects a DC output side of the line-side diode rectifier with a DC input side of the load-side inverter. A buffer capacitor is connected across the power supply, and a decoupling diode and a current limiting circuit are electrically connected in series with the buffer capacitor. The serially connected buffer capacitor, decoupling diode and current limiting circuit are connected in parallel with the DC link capacitor. This arrangement results in a voltage source converter that has an improved service reliability even in unstable power grids, without adding circuit complexity to the line input.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.

Abstract: For one or more disclosed methods, a supply voltage is supplied to an integrated circuit, the integrated circuit is placed in a test mode to select one of a plurality of reference voltage generators on the integrated circuit to supply to another voltage generator on the integrated circuit a reference voltage that is at least partially dependent on the supply voltage, and the integrated circuit is tested with the reference voltage supplied to the other voltage generator.

Abstract: A semiconductor device having a delay drift compensation circuit that compensates for a delay drift caused by temperature and voltage variations in a clock tree includes a clock driver having an output port, a first circuit having an input port, a first signal path between the output port of the clock driver and the input port of the first circuit and a first delay drift compensation circuit. The first delay drift compensation circuit, which is coupled with the first signal path, reduces a delay time of the first signal path when a power supply voltage increases, and increases the delay time of the first signal path when a temperature increases.

Abstract: The invention relates to a method of establishing a PWM-modulated output signal representation (OS), providing a stream of parallelly determined intersection representations (PIR) on the basis of a stream of parallel reference signal representation (PRSR) and an input signal (IS), establishing a serial PWM output signal representation (OS) by transforming said stream of parallelly determined intersection representations (PIR) into a stream of serial intersection representations (SIR) by means of a relative time shift of at least one of said parallelly determined intersections (PIR). According to an embodiment of the invention, an advantageous way of providing intersection estimates has been obtained, as each or at least a number of intersection estimates between a reference signal and an input signal may be established partially while taking only the individual partial reference functions into consideration.

Abstract: When a signal of a double frequency is generated from the original signal, conventionally a 90-degree phase-shift circuit is necessary to suppress an output of a DC component and efficiently obtain a double wave. According to the present invention, an equal RF signal is inputted to input terminals and an output is matched with a frequency as high as that of the original frequency in a Gillbert cell double-balanced mixer, so that a doubled output is obtained with no DC offset. According to the circuit configuration of the present invention, it is possible to provide a circuit readily performing integration and to efficiently output only a double frequency merely by inputting a simple differential signal without the need for the original signal which has been phase controlled. Further, a DC short circuit in the resonance circuit makes it possible to eliminate a DC offset voltage in an output.

Abstract: Provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section A and a reference potential section GND. Further provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line B arranged in parallel to the signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section B and a reference potential section GND.

Abstract: A PLL circuit is described. The PLL circuit includes: a signal generator and at least one divider coupled to the signal generator, where the at least one divider is programmable in user mode. In one embodiment, the PLL circuit includes a memory device associated with the at least one divider, where the memory device receives settings data and provides settings data to the at least one divider in user mode.

Abstract: A drive circuit for a voltage driven type semiconductor element, includes: an electrical charge discharge unit that discharges electrical charge from a gate terminal of a voltage driven type semiconductor element when the voltage driven type semiconductor element is turned OFF; and an electrical discharge control unit that detects a time variation of a collector voltage of the voltage driven type semiconductor element, and controls electric discharge by the electrical charge discharge unit according to the time variation of the collector voltage which has been detected.

Abstract: A frequency monitor circuit (FMC) that is part of an integrated circuit chip for monitoring the frequency of one or more clocks present on the chip is disclosed. The FMC includes a reference window generator, operative to output a reference window signal of a given duration, and a clock counter, operative to count all pulses, in any one of the clocks, that occur within the duration of the reference window and to output a corresponding pulse count. The FMC further includes two or more comparators, each operative to compare the pulse count with a respective given threshold value and to output a corresponding indication of frequency deviation. In one configuration, in which the clock is generated on the chip by a frequency multiplier, the reference window generator and the clock counter are shared between the frequency monitor circuit and the frequency multiplier.

Abstract: A data processing chip with a flexible timing system and method for supplying clocks to a digital data processing system useful for power conservation. A phase locked loop generates a master clock from which a core clock and a system clock are derived. The frequency of each of the core and system clocks is independently controllable relative to the master clock and can be changed on the fly with glitch free and jitter free operation. The data processing chip is well suited for use in hand held electronic devices where power management is a concern. Power can be saved by lowering the frequency of the core clock, even for short intervals of time.

Abstract: An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.

Abstract: We describe and claim an internal signal replication device and method. A circuit comprising a selector to select one of a plurality of internally generated clock signals, and a compensation circuit to replicate the selected clock signal from a reference clock signal.

Abstract: Circuitry and methods are provided for continuously adjustable frequency synthesis. The synthesis covers a wide range of possible frequencies and can be performed to a high degree of precision. In an embodiment of the invention, an analog phase-locked loop (“PLL”) performs relatively coarse wide-range frequency synthesis, while a digital PLL performs relatively fine narrow-range frequency synthesis and phase alignment. The analog PLL is capable of varying frequency in a stepwise linear fashion. The digital PLL communicates with the analog PLL to ensure that the output of the analog PLL is within the digital PLL's specified pull-in range.

Abstract: An integrated differential receiver includes a single gate oxide differential receiver and an associated switchable voltage supply circuit. The integrated differential receiver determines the desired receiver supply voltage and selects a supply voltage for the single gate oxide differential receiver. When a lower supply voltage is determined as the desired supply voltage, the integrated differential receiver automatically provides a supply voltage to the single gate oxide differential receiver with a voltage higher than the I/O pad supply voltage and higher than the maximum input signal voltage to increase the speed of operation for the differential receiver. The switchable voltage supply circuit is operatively responsive to a control signal which indicates the desired supply voltage for the I/O pad. In one embodiment, both the single gate oxide differential receiver and the switchable voltage supply circuit are single gate oxide circuits.

Abstract: A semiconductor memory device includes memory modules which have memories and a data bus which transfers data to the memory modules, in which the data bus comprises a low frequency band data pass unit which removes the high frequency component of the data and sends the data to the memory modules. The low frequency band data pass unit comprises a plurality of stubs which are connected to the data bus in parallel and are formed as printed circuit board (PCB) patterns. The low frequency band data pass unit comprises a plurality of plates that are connected to the data bus in parallel and are formed as PCB patterns. The low frequency band data pass unit has a shape in which parts having a wide width and parts having a narrow width are alternately connected.