Abstract: A clock frequency divider circuit including: a storing section for storing an input signal in synchronism with an input clock signal; a supplying section for supplying, as the input signal, one of a first value obtained by adding a value stored by the storing section to a numerator setting value and a second value obtained by subtracting a denominator setting value from the first value; a retaining section for retaining a most significant bit of the value stored by the storing section in synchronism with the input clock signal; and a logical product generating section for generating a logical product of a value retained by the retaining section and the input clock signal, and outputting the logical product as an output clock signal; wherein the supplying section supplies one of the first value and the second value as the input signal on a basis of the most significant bit of the value stored by the storing section.

Abstract: A method and apparatus for controlling a voltage generator of a memory device are provided. In one embodiment, a first clock signal and a second clock signal are provided. The voltage generator is selectively enabled in conjunction with the first clock signal when a period of the first clock signal is less than a period of the second clock signal and the voltage generator is selectively enabled in conjunction with the second clock signal when the period of the second clock signal is less than the period of the first clock signal.

Abstract: Methods and systems for reducing effects of digital loop dead zones add phase randomness to one or more asynchronous signals that are to be synchronized with a digital loop system clock. Phase randomness is added in one or more of a variety of ways including, without limitation, non-harmonic asynchronous signals and variable phase delay. The invention can be implemented in a variety of types of digital loops including, without limitation, phase locked loops (“PLLs”). For example, a PLL receives a system clock signal, a digital reference signal, and a feedback signal. The digital reference signal and/or the feedback signal is asynchronous with the system clock signal. A phase of the asynchronous signal(s) is randomized and then synchronized with the system clock signal, prior to phase difference detection. This reduces effects of digital loop dead zones that are otherwise introduced by synchronization.

Abstract: In a delay locked loop and a semiconductor memory device having the same, the delay locked loop includes a phase detecting and control signal generator for detecting a phase difference between a clock signal and a feedback clock signal and generating a plural-bit delay control signal which varies according to the phase difference; a first delay having a predetermined number of first delay cells which are cascade-connected for delaying the clock signal to generate a plurality of output clock signals and the feedback clock signal in response to the plural-bit delay control signal; a second delay having a predetermined number of second delay cells which are cascade-connected for delaying an inverted clock signal to generate a plurality of inverted output clock signals in response to the plural-bit delay control signal; and a phase mixer for phase-mixing corresponding clock signals among the plurality of output clock signals and the plurality of inverted output clock signals to output a plurality of corrected out

Abstract: A multiphase resonant pulse generator (74) has N groups of N?1 switches (44,46,48) which, when activated, form N paths from a power supply (Vdc) to ground or a reference voltage. Here N is a positive integer greater than 2. Each of the paths includes an inductance (38,40,42) and N?1 switches. The signal outputs (X1,X2,X3) from each of the N paths are cross coupled to switches belonging to the other N?1 paths to active or deactivate the groups of switches.

Abstract: By forming adjacent wiring 4 adjacent to signal wiring 3 and using a control circuit 13 comprising a 2-input NAND 20 circuit or the like to input a signal S4 corresponding to a signal S3 in the signal wiring 3 to the adjacent wiring 4, it is made possible to change the delay of the signal S3 in the signal wiring 3 in several picoseconds, by using crosstalk with the signal S4 in the signal wiring 4.The inventive delay control circuit device can be provided by simply adding adjacent wiring 4 and a control circuit 13 to signal wiring 3. This implements a delay control circuit device for semiconductor integrated circuits that is capable of controlling a signal delay in several picoseconds without increasing the circuit scale.

Abstract: A power-on bias circuit including a first inverter having an input terminal and an output terminal, the input terminal functions as an input terminal of the power-up bias circuit; a second inverter having an input terminal and an output terminal, the output terminal of the second inverter functions as the output terminal for the power-on bias circuit; and a Schmitt Trigger circuit having an input terminal and an output terminal, wherein the input terminal of the Schmitt Trigger circuit is connected to the output terminal of the first inverter, the output terminal of the Schmitt Trigger circuit is connected to the input terminal of the second inverter, the first inverter, the second inverter and the Schmitt Trigger circuit are each in electrical communication with a voltage input terminal and ground.

Abstract: A phase detector includes a first flip flop having a data input coupled to a first clock signal at a first frequency and a clock input coupled to a second clock signal at a second frequency. The frequency of the first clock signal is a multiple of the frequency of the second clock signal. The phase detector also includes a second flip flop having a data input coupled to an output of the first flip flop and a clock input coupled to the second clock signal.

Abstract: There is provided a Delay Locked Loop (DLL) including a duty cycle correction circuit capable of controlling a duty error, when the duty error is generated in the DLL. The duty cycle correction circuit controls amounts of electric charges accumulated in storage units, in response to switching control signals received from the external, and outputs duty rate control signals each corresponding to a difference between the amounts of electric charges accumulated in the storage units. Therefore, the DLL including the duty cycle correction circuit can correct a duty cycle of a reference clock signal, in response to the duty rate control signals, and can output a reference clock signal with a duty cycle of 50%.

Abstract: A chopped charge pump with matching up and down pulses including a first pair of current sources, a second pair of current sources, and a switching circuit for switching on in a first phase one current source of each pair to provide up current pulses, and the other current source of each pair to provide down current pulses, and switching on in a second phase the other current source of each pair to provide up current pulses, and the one current source of each pair to provide down current pulses to offset error in the current response of the pairs of current sources.

Abstract: A DPC (200) that includes: a frequency source (20); a delay-locked loop (220) for receiving a clock signal and generating a plurality of phase-shifted clock signals; a control device (280) having a DPS (282) and a DAC (284) for receiving an input signal identifying a desired frequency for a synthesized signal; a selection circuit (270) for receiving the plurality of phase-shifted clock signals, selecting a sequence of the phase-shifted clock signals and outputting a coarse synthesized signal; a variable delay cell (290) having a first input coupled to the selection circuit to receive the coarse synthesized signal and a second input coupled to the control device for receiving a fine tune adjustment signal to modify the coarse synthesized signal to generate the synthesized signal (292) having substantially the desired frequency. The DPC further includes training apparatus for calibrating the DPC.

Abstract: A bandgap circuit comprising a current generation circuit and a current replication circuit is provided herein. The output current of the current generation circuit is generated as a weighted sum of two currents. The circuit configuration of the current generation circuit allows it to function at low power supply voltages, e.g., on the order of 1 V. The current replication circuit includes an operational amplifier, which when configured in conjunction with MOS cascode current sources and the current generation circuit, significantly increases the accuracy and insensitivity to power supply noise of the bandgap circuit output current. A resistor may be included between the bandgap circuit output node and ground for generating a reference voltage with increased accuracy and insensitivity to power supply noise.

Abstract: A semiconductor switch comprises two NMOS transistors coupled in an anti-series arrangement, and a gate control circuit coupled to both gates of the NMOS transistors. Both drains of the NMOS transistors are interconnected, and the gate control circuit is coupled to the drains interconnection. The required chip area is halved compared to prior art switches. Pumping the gates to higher voltages may cause a further reduction of the sizes of the NMOS transistors. In addition, advantageously, a large range of input and output voltages can be allowed between the sources of the NMOS transistors, whereby the sources act as input and output respectively of the switch, thus allowing application of the switch in a broad technical field.

Abstract: A circuit comprises an off chip driver and a delay locked loop. The delay locked loop is configured to receive a clock signal and provide a first signal for compensating for a rising edge propagation delay through the off chip driver and a second signal for compensating for a falling edge propagation delay through the off chip driver. The off chip driver is configured to receive the first signal and the second signal and output data aligned with the clock signal.

Abstract: Delay locked loops include a ring oscillator having serially connected inverters and a feedback path around the serially connected converters. The ring oscillator is configured to generate an output clock signal that is a delayed version of an input clock signal, in response to the input clock signal and to a control signal that is applied to the ring oscillator. A phase responsive circuit is configured to generate the control signal in response to a phase difference between the input clock signal and the output clock signal. Analogous methods of delaying a clock signal also are described.

Abstract: A DLL voltage supply device for use in a semiconductor memory device includes: a bandgap voltage generating means for generating a bandgap voltage by using an external power supply voltage; a voltage level shifter for increasing a voltage level of the bandgap voltage in order to output an increased bandgap voltage as a DLL voltage; and a voltage level keep means for outputting the external power supply voltage as the DLL voltage if the increased bandgap voltage is lower than a predetermined voltage level.

Abstract: The present invention discloses a delay-locked loop device capable of anti-false-locking, which comprises: a voltage control delay circuit comprising a plurality of delay units in a series for generating a delayed phase according to a reference phase and a control voltage; a phase detector coupled to the voltage control delay circuit for generating a control signal according to a lock indication signal, the reference phase, and the delayed phase; a charge pump coupled to the phase detector for transmitting the control voltage to the voltage control delay circuit according to the control signal; and a lock detector coupled to the voltage control delay circuit for generating the lock indication signal for the phase detector according to output phases of at least one delay unit of the voltage control delay circuit.

Abstract: A method for generating short electric pulses, comprising the steps of generating a control pulse, feeding the control pulse to a bipolar transistor, which subsequently emits an output signal with a steep switch-off side by exploiting the charge storage effect of the bipolar transistor, and differentiating the output signal with the steep switch-off side so that short primary pulses are generated. An electric pulse generator is also disclosed.

Abstract: A rectifier circuit is provided, which does not need a feedback function and prevents deterioration of a frequency characteristic, even if the rectifier circuit is configured with thin film transistors (TFTs). For example, the rectifier circuit is configured with an amplifier circuit, which compares an input signal with a voltage of a power source; a waveform shaping circuit for shaping a waveform of an output signal of the amplifier circuit; a resistor, which is connected to both an input terminal and output terminal; and a switching circuit, which is connected to both the output terminal and the power source, and is controlled by an output signal of the waveform shaping circuit. Then, either the input signal or the voltage of the power source is outputted in accordance with an operation of the switching circuit, so that the input signal is ideally rectified.

Abstract: An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T1) and a second branch including a charge pump (10) and a second controllable resistance (T2) are connected between the input terminal (IN) and the output terminal (A). A control circuit (20) alters the resistance values of the first and second controllable resistances (T1, T2) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.