Abstract: High resolution digital delay circuits and methods are provided. A multiplexer receives the outputs of first and second delay elements. At least the second delay element is adjustable using a digital control signal. The multiplexer and the first delay element form a first delay loop. The multiplexer, the first delay element and the second delay element form a second delay loop. A logic circuit monitors the number of times (M) that a signal cycles through the first loop. After M reaches a predetermined value (i.e., when the signal is delayed by a predetermined delay), the multiplexer receives a control signal that causes the second loop to close. A signal cycles through the second loop, which provides additional delay. Preferably, the signal cycles through the second loop only once. Generally, this causes the resolution of the delay circuit to be proportional to the minimum delay adjustment of the second delay element.

Abstract: A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

Abstract: A pulse width measurement system is provided with components in an FPGA so that pulse widths can be measured that are smaller than the frequency limits of the FPGA system clock. For the measurement, an incoming pulse is fed into the FPGA to many (e.g. 32) I/O inputs in parallel. Each parallel input is then provided to a programmable delay device with each delay configured to a different ascending delay value. The input transition time is then detected by converting the outputs from the delay devices into data indicating the timing information. In one embodiment the outputs of the delay devices address data stored in BRAMs for later processing in the FPGA to determine the timing information.

Abstract: An improved clock lock detection circuit is disclosed. The circuit has a first input indicating an edge of a first clock and a second input indicating a corresponding edge of a second clock wherein the second clock is expected to be synchronized with the first clock with an allowable time difference. Further, it has a difference generation module for generating a difference signal based on the time difference between the first and second inputs, and a voltage divider module for receiving the difference signal and generating an indication voltage which varies based on a change of the time difference between the first and second inputs.

Abstract: The present invention relates to the field of electronics. More particularly, forms of the present invention relate to systems, methods and circuits for generating a signal. A system, method and circuit for generating a signal are described. Forms of this system, method and circuit provide clock duty cycle improvement with no frequency reduction. Some such forms provide a clock signal approaching or achieving 50 percent with no significant frequency departure, reduction, etc. from a generated clock. One form of the present invention uses two similar clock signals that oscillate at the same frequency, but effectively inverted one from another. In one such form, the inverted signals are generated with a voltage controlled oscillator having differential stages.

Abstract: A method and circuit for driving the gate of a MOS transistor having a negative or low threshold voltage negative, in which the driving circuit is formed on a single chip. A negative voltage is generated from a positive voltage to drive the gate of the MOS transistor negative. The MOS transistor may be a native NMOS transistor, and the negative voltage is generated for increasing source-drain impedance of the native NMOS transistor. On the other hand, the MOS transistor may be a PMOS transistor, and the negative voltage is generated for reducing source-drain impedance of the PMOS transistor. The MOS transistor can be used as an open-drain switch or a source follower.

Abstract: A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the first signal and the at least one selected version of the first signal. The method also includes generating multiple delayed versions of the second signal using at least one second delay line, and selecting at least one version of the second signal. In addition, the method includes modifying selection of the at least one version of the first signal and the at least one version of the second signal to achieve a desired output signal based on the at least one selected version of the second signal. This method could be used in various circuits, such as duty cycle correction circuits, frequency multiplier circuits, and digital multiphase oscillator circuits.

Abstract: A voltage regulator has a reference voltage generator that outputs a reference voltage based on first and second electrical source voltages, an output circuit which generates a predetermined direct-current voltage based on the reference voltage and generates a comparison voltage lower than the predetermined direct-current voltage, and a differential amplifier coupled between the reference voltage generator and the output circuit. The differential amplifier provides a control voltage to the output circuit responsive to a difference between the reference and comparison voltages. The voltage regulator has a voltage adjustment circuit that adjusts the reference voltage responsive to a variation in the first electrical source voltage. The differential amplifier may include a constant-current circuit and an operation current generating circuit.

Abstract: The method provides wide-range delay value adjustment without making changes in cell size and metal wiring, even when a process variation occurs. Threshold values of some or all of the transistors which form the delay gate inserted into the signal path are varied to control the delay value of the delay gate, so that the delay value of the signal path is adjusted.

Abstract: Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using calibration circuits. Each calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When the effective resistance of the group of transistors matches the external resistance, the calibration circuit causes the effective resistance of drive transistors in the IO buffer to match the effective resistance of the group of on-chip transistors.

Abstract: A system and method is provided for extending the range of a common mode voltage of a differential comparator. In one embodiment, a differential comparator comprises an input stage with a negative voltage reference node, a first differential input coupled to a first differential pair transistor and operative to receive a first input signal, and a second differential input coupled to a second differential pair transistor and operative to receive a second input signal. The first input signal and the second input signal form a differential input signal. The differential comparator further comprises a common mode sensing circuit interconnected between the first differential input, the second differential input, and the negative voltage reference node. The common mode sensing circuit is operative to sense a common mode voltage of the differential input signal and set a voltage potential at the negative voltage reference node substantially equal to the sensed common mode voltage.

Abstract: A delay-locked loop (“DLL”) having reduced susceptibility to false lock. The DLL includes a delay path coupled to delay an input signal. The delay path includes two or more variable delay cells coupled in series and a feedback node coupled to an output of one of the variable delay cells. An inverter is coupled to receive the input signal and to output an inverted signal. A feedback circuit is coupled to receive the inverted signal from the inverter and to receive a feedback signal from the feedback node. The feedback circuit monitors a phase difference between the inverted signal and the feedback signal to generate a delay control signal in response to the phase difference to adjust a variable delay of the delay path.

Abstract: Integrated circuit device includes: a wiring; a clock signal output circuit including a ring oscillator; an internal circuit; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit; and a capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.

Abstract: A circuit for and method of operating a supply tracking clock multiplier is provided. An embodiment of the present invention may permit a less power consuming portion of an integrated circuit to operate at a relatively higher average clock rate than a more power consuming portion operating at a relatively lower clock rate, by adjusting the duration of the cycles of the higher frequency clock. The adjustment may be according to the supply voltage changes that result from logic switching activity of the more power consuming portion, and may be performed in a manner that substantially matches the delay behavior of the logic. The phase of the higher frequency clock remains locked to the lower frequency clock. An embodiment of the present invention may reduce the area and cost of an integrated circuit by minimizing the need for other on-chip power supply noise mitigation approaches, while also improving device throughput and performance.

Abstract: A divider to divide a frequency Fe comprises at least the following elements: three flip-flop circuits, each of the flip-flop circuits receiving the frequency to be divided, every feedback loop between an output of a flip-flop circuit and its input or the input of the other flip-flop circuits comprising a single multiplexer, wherein one of the flip-flop circuits commands the loading of all the flip-flop circuits during one period of the frequency A multiplexer has two inputs, one selection bit and one output and is integrated into a flip-flop circuit.

Abstract: Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using a calibration circuit. The calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When voltage between the external resistor and the group of transistors is within a selected range, the calibration circuit causes the effective resistance of the transistors to match the resistance of the external resistor as closely as possible. The calibration circuit enables another set of transistors in the IO buffer so that the effective on resistance of the transistors in the IO buffer closely match the resistance of the external resistor.

Abstract: Methods and apparatuses are discussed for generating a temperature compensated signal, used for example to provide a signal with a delay within a pre-specified range over a range of temperatures to a sense amplifier of a memory array. In response to a start signal, a varying signal is generated. A clock signal causes additional loads of impedance to be coupled to the varying signal, for example via control circuitry generating temperature compensating signals.

Abstract: A start signal outputting circuit according to the invention has a differential RF/DC convertor part 100 for converting a high frequency power (RF) into a d.c. potential (DC). The RF/DC convertor part 100 is formed by two transistors QRD, QDD working as a diode, and transistors QR1˜R3, QD1˜D3 and resistances RR1˜R3 for forming high resistances at anode sides and cathode sides of these diodes, respectively. A differential amplification part 200 disposed at a later stage of the diode has not only amplifying effect but also low-pass filtering effect together with filtering pars 120, 210 of its previous and later stages. In this case, it is designed so that current flowing through the respective circuits is about 2˜3 ?A. As a result, even if the high frequency power of the specified frequency is weak, for example ?60˜?40 dBm, a start signal outputting circuit 1000 which outputs a d.c. potential of 0.3˜2.4V, is suitable for integration and has a low power consumption can be obtained.

Abstract: A DLL circuit includes a phase comparator configured to compare timing between a first clock signal and a second clock signal, a delay circuit configured to delay the first clock signal for output as the second clock signal by a delay length responsive to a result of comparison by the phase comparator, and a control circuit configured to suspend supply of the first clock signal to the phase comparator temporarily while the second clock signal is supplied to the phase comparator.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.