Patents Examined by Toan Tran
  • Patent number: 7482861
    Abstract: A power MOSFET Qp and a protection circuit 3 are formed over a semiconductor substrate to constitute a construction in which the power MOSFET Qp and the protection circuit 3 are electrically separated from each other. Then, a screening voltage is applied between the gate electrode and the source electrode of the power MOSFET Qp which is electrically separated from the protection circuit 3, thereby eliminating a power MOSFET Qp having a latent defect. Subsequently, a non-defective power MOSFET Qp and the protection circuit 3 are electrically connected by a bonding wire.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: January 27, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Fujiki, Tetsuo Iijima
  • Patent number: 6836607
    Abstract: An optically active fiber (30) is disclosed for making a fiber laser (18) or an amplifier (16). This double-clad structured active fiber (30) has a core (34), doped with an optically excitable ion having a three-level transition. The core (34) has a core refractive index and a core cross-sectional area. An inner cladding (32) surrounds the core (34). The inner cladding (32) has an inner cladding refractive index less than the core refractive index, an inner cladding cross-sectional area between 2 and 25 times greater than that of the core cross-sectional area, and an aspect ratio greater than 1.5:1. An outer cladding (36) surrounds the inner cladding (32) and has an outer cladding refractive index less than the inner cladding refractive index.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: December 28, 2004
    Assignee: Corning Incorporated
    Inventors: Matthew J. Dejneka, Adam J. Ellison, Dmitri V. Kuksenkov, John D. Minelly, Carlton M. Truesdale, Luis A. Zenteno
  • Patent number: 6737899
    Abstract: Techniques to improve the operating speed and switching performance of a latch having an integrated gate. In one design, the latch includes first and second differential amplifiers and a feedback circuit (e.g., a third differential amplifier). The first differential amplifier has a number of non-inverting inputs (e.g., configured to implement an OR function) and an inverting input, receives and senses input signals applied to the non-inverting inputs during a “sensing” phase, and provides a differential output. The second differential amplifier latches the output during a “latching” phase. The feedback circuit detects the non-inverting output and provides a control signal for the inverting input of the first differential amplifier. The feedback circuit can provide positive feedback, and can dynamically adjust the inverting input to provide improved switching performance.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: May 18, 2004
    Assignee: Resonext Communications, Inc.
    Inventor: Douglas Sudjian
  • Patent number: 6714055
    Abstract: The invention features an output driver device for an integrated circuit that includes an output device having an output terminal for an output signal to be output from the output driver device, an input terminal for an input signal to be input into the output driver device, and a control device that is signal-connected to the output device and the input terminal and is designed to transform the input signal into two mutually different control signals and to output the control signals via control signal outputs to the output device, where the output device configured to generate the output signal in a manner dependent on the control signals.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: March 30, 2004
    Assignee: Infineon Technologies AG
    Inventor: Michael Hausmann
  • Patent number: 6686782
    Abstract: A power supply voltage detection circuit includes a voltage division circuit for linearly dividing a power supply voltage, a reference voltage circuit for providing a reference voltage, and a comparison circuit for comparing the output voltage from the voltage division circuit and the reference voltage from the reference voltage circuit. The power supply voltage detection circuit outputs a signal upon detecting that the power supply voltage is equal to or higher than the reference voltage. A PMOS transistor is provided between the voltage division circuit and the comparison circuit. The PMOS transistor includes a source terminal connected to an output terminal of the voltage division circuit, a drain terminal connected to an input terminal of the comparison circuit, and a gate terminal connected to the ground.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: February 3, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masayoshi Kinoshita, Jun Kajiwara, Shiro Sakiyama
  • Patent number: 6683487
    Abstract: An H-type bridge circuit includes four transistors, two resistors, and a write head. A write current supplied from a current supply circuit including a first of the transistors and resistors flows through the write head and is received in a current receiving circuit including a second of the resistors and a fourth of the transistors, and another write current supplied from a current supply circuit including the second of the transistors and the second resistor flows through the write head and is received in a current receiving circuit including the first of the resistors and the third of the transistors. Impedance of the write head matches an output impedance of the current supply circuit and matches an input impedance of the current receiving circuit.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: January 27, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toru Takeuchi, Takehiko Umeyama
  • Patent number: 6667650
    Abstract: A leakage compensation circuit and technique is provided that compensates for losses in a referenced current of an amplifier circuit due to leakage elements. The leakage compensation circuit is configured to inject current substantially equal in magnitude to the leakage current into one or more junctions of the amplifier circuit to compensate for lost referenced current due to leakage. As a result, the amplifier circuit and various devices can realize the flow of the reference current as substantially intended without detrimental effects of leakage current, thus maintaining the integrity of the referenced current. The leakage compensation circuit comprises an array of compensation regions configured to approximate the collective loss that is created by the leakage elements and provide a compensation current substantially equal in magnitude to one or more junctions to compensate for lost referenced current.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: December 23, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: David A. Gammie, Jeffrey B. Parfenchuck, David M. Jones, Jerry L. Doorenbos
  • Patent number: 6664814
    Abstract: A circuit and method for driving the output signal, having a common-mode voltage and an output swing, of an integrated circuit. In accordance with an aspect of an embodiment of the present invention, a first power supply provides the termination voltage for the output signal and a second power supply provides the power to set the common mode voltage. In accordance with another aspect, the common-mode voltage and the output swing are programmable.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: December 16, 2003
    Assignee: Cadence Design Systems, Inc.
    Inventors: William P. Evans, Luca Ravezzi, Alberto Baldisserotto
  • Patent number: 6664823
    Abstract: An inverter output circuit comprises first though third inverters connected in series. The low-potential output of the first inverter has an offset level. The input threshold voltage of the second inverter is set up at a lower level than the low-level offset potential of the first inverter as the level of supply voltage Vdd falls below a predetermined reference level. Thus, the third inverter is fixed to a predetermined condition if the supply voltage drops below the reference voltage, thereby preventing erratic operations of a load connected to the inverter output circuit caused by, for example, a power shut down and a brownout.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: December 16, 2003
    Assignee: Rohm Co., Ltd.
    Inventor: Shizuka Yokoi
  • Patent number: 6661260
    Abstract: An output circuit of a semiconductor circuit includes a higher potential side power supply line, a output signal line on which an output signal is outputted, a control signal line on which a control signal is transferred, a gate signal line on which a gate signal is transferred, an output transistor, a first switch and a gate driving circuit. The output transistor is connected between the higher potential side power supply line and the output signal line to operate in response to the gate signal on the gate signal line. The first switch is connected to the higher potential side power supply line to turn off in response to the control signal of a first state and turn on in response to the control signal of a second state. The gate driving circuit is connected between the first switch and the control signal line to generate the gate signal onto the gate signal line based on a gate control signal when the first switch is turned on.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: December 9, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Akihiro Nakahara, Akio Tamagawa
  • Patent number: 6657475
    Abstract: A DC voltage bus clamp includes a transistor, a resistor, and a diode. The transistor is placed in parallel with a load. The resistor is connected across a bridge rectifier. A gate or base of the transistor is connected to the resistor. The anode of the diode is connected to ground and the cathode is connected to the gate or base of the transistor. A hysteresis circuit may be added to form a second embodiment of the DC voltage bus clamp to trigger the transistor suddenly. A third embodiment of the DC voltage bus clamp includes a resistor sensing circuit. The diode of the first embodiment is replaced with a sense resistor. The resistor sensing circuit is connected between the sense resistor and the transistor.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: December 2, 2003
    Inventor: David L. Zahn
  • Patent number: 6657471
    Abstract: An improved pull-down latch circuit is provided for better latch performance. Previous pull-down latch circuit performance is compromised during pull-up operation since weak PFETs are employed to pull up latch nodes. A pull up assist circuit is incorporated to assist weak PFET when latch node is being pulled up. The assist circuit is isolated from latch circuit when latch node is being pull down to guarantee that pull down circuit can overcome pull-up circuit (for correct latch operation).
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: December 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: Brian W. Curran, Edward T. Malley
  • Patent number: 6653882
    Abstract: The invention features an output driver for integrated circuits that includes a driver that has a data input connected to the integrated circuit, a data output connected to a transmission line leading to the external circuit, and impedance adjusting means for adjusting the output impedance of the driver circuit according to determinable impedance adjusting data. The output driver also includes a dummy circuit having a dummy driver circuit and transmission line, and an impedance control circuit for controlling the output impedance of the driver circuit. The impedance control circuit controls the impedance of the driver circuit by determining the impedance adjusting data (necessary for matching the output impedance of the dummy driver circuit to the characteristic impedance of the dummy transmission line and outputting the determined impedance adjusting data to the impedance adjusting means of the driver circuit.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: November 25, 2003
    Assignee: Infineon Technologies AG
    Inventor: Arindam Raychaudhuri
  • Patent number: 6650158
    Abstract: Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: November 18, 2003
    Assignee: Ramtron International Corporation
    Inventor: Jarrod Eliason
  • Patent number: 6650170
    Abstract: According to some embodiments, a drive circuit provides an output resistance substantially stable despite variations in operating temperature.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: November 18, 2003
    Assignee: Intel Corporation
    Inventor: Lawrence S. Uzelac
  • Patent number: 6646486
    Abstract: The semiconductor integrated circuit includes a first transistor which flows a current from a high voltage source to a first node, a second transistor which flows a current from the first node to a low voltage source. Furthermore, a first inverter receives an input signal and drives the first node based on this input signal, and a second inverter drives a second node based on a voltage of the first node.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: November 11, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Uchiki, Harufusa Kondoh
  • Patent number: 6646487
    Abstract: The invention relates generally to the field of electronic circuit design, and in particular to techniques for reducing hazards in a digital logic circuit, for example, a digital logic flip-flop circuit. In an embodiment of the present invention a method for reducing hazards in a flip-flop, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. First, the pre-charged stage sets the internal node based on a data input. The evaluation stage is prevented from evaluating the internal node for a predetermined time period. After the predetermined time period, the internal node is evaluated by the evaluation stage to determine an output of the flip-flop.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: November 11, 2003
    Assignee: Fujitsu Limited
    Inventors: Nikola Nedovic, Vojin G. Oklobd{haeck over (z)}ija, William W. Walker
  • Patent number: 6646479
    Abstract: A non-delayed input signal is provided to a first comparator input and, a delayed input signal is applied to a second comparator input. An offset voltage is applied between the delayed and non-delayed signals at the comparator inputs. When an input pulse appears on the input signal, the non-delayed input signal will rise immediately and maintain itself more positive than the delayed input, keeping the comparator output inactive. As long as the input signal is rising, the comparator output is maintained low, or inactive. When the non-delayed signal reaches its peak and turns downward, the delayed input signal is still rising and crosses over the first pulse, creating a change of state at the comparator output to a high or active state. The signal edge resulting from this change of start represents initial detection of an input pulse. The time of occurrence of this detection edge is substantially independent of the pulse amplitude.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: November 11, 2003
    Assignee: Analog Modules Inc.
    Inventor: Ian D. Crawford
  • Patent number: 6642767
    Abstract: DC offset canceling is disclosed. A DC level fixing signal generator receives feedback input of two output signals from a mixer and generates a level fixing control signal to fix the DC level of the two output signals according to the input values. A DC offset canceling signal generator receives feedback input of two output signals from the mixer and generates offset canceling control signals to cancel the relative difference between the DC levels of the two output signals according to the input values. A DC level fixing and offset canceling circuit fixes the DC level of each of the two output signals from the mixer and cancels the relative difference between the DC levels of the two output signals according to the level fixing control signal and the offset canceling control signals.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: November 4, 2003
    Assignee: Berkana Wireless, Inc.
    Inventor: Sung-ho Wang
  • Patent number: RE38455
    Abstract: Integrated circuitry for selectively introducing capacitance and for controlling the transconductance transfer function of one or more amplifiers includes concatenated differential amplifiers with one or more pairs of switchable capacitive components differentially connected across outputs of the differential amplifiers to facilitate operation over a wide range of operating frequencies under control of external signals.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: March 9, 2004
    Assignee: Marvell International, Ltd.
    Inventors: Sehat Sutardja, Pantas Sutardja