Abstract: The invention relates to a balanced circuit arrangement for converting an asymmetric analogous input signal (S1) into a symmetrical output signal (S2, S3). A first amplifier (2) is provided, whereby the non-inverting input thereof is connected to the analogous input signal (S1) and the output signal (S2) thereof is fed back to the inverting input thereof in a negative feedback. Moreover, a second amplifier (3) is provided, whereby the non-inverting input thereof is connected to ground, the inverting input thereof is connected to the output signal (S2) of the first amplifier (2) by means of a series resistor (R2) and the output signal (S3) thereof is fed back to the inverting input thereof in a negative feedback and by means of a negative feedback resistor (R1). The negative feedback resistor (R1) and the series resistor (R2) are provided with the same resistance value. The aim of the invention is to process higher maximum levels of the source signal and to suppress noises of the second amplifier.

Abstract: The polyphase signal generator includes a first delay circuit which adds a first predetermined phase delay to an input signal, a first phase interpolation circuit which generates a first output signal having an output phase prescribed according to a phase difference between the input signal input to one terminal of the first output signal generation unit and a signal input to another terminal of the first output signal generation unit which is output from the delay addition unit, and a second phase interpolation circuit which generates a second output signal having an output phase prescribed according to a phase difference between a signal input to one terminal of the second output signal generation unit which is output from the delay addition unit and an inverted signal of the input signal input to another terminal of the second output signal generation unit.

Abstract: A level shift circuit for shifting an input voltage to an output voltage is provided. The level shift circuit includes at least a complementary metal oxide semiconductor (CMOS) transistor formed on a p-substrate. The CMOS transistor has a PMOS transistor and an NMOS transistor. The NMOS transistor includes a gate electrode, a drain electrode having an n-well formed on the p-substrate and a first n-doped region formed inside the n-well, and a source electrode having a second N-doped region formed on the p-substrate.

Abstract: A sense amplifier having three inputs determines the state of a memory bit cell by converting a bit input voltage, a high reference voltage, and a low reference voltage to respective current values. Current differences are formed between a bit current and a high reference current, and between a low reference current and a bit current. Current mirrors (154, 158 and 170, 166) and loads (160 and 168) are used in conjunction with current steering circuitry (150, 140, 142 and 162) to form the difference of the bit current and the high reference current and also form the difference of the low reference current and the bit current. Additionally, the sense amplifier drives differential outputs (OUT and OUT13B) to reflect the difference between the two current differential quantities.

Abstract: The invention provides apparatus, methods and systems for providing voltage protection at the drain-to-source path of an output transistor. The invention discloses circuit apparatus and system giving excess voltage protection in a circuit having a voltage swing up to approximately twice the voltage capacity of a circuit output transistor. Methods of the invention disclose maintaining the source-to-drain voltage of a protection transistor coupled to the circuit output transistor below its maximum value, while also maintaining the protection transistor gate-to-source voltage below its maximum value. The drain-to-source voltage of the circuit output transistor is guarded from exceeding its maximum acceptable drain-to-source voltage value by the protection transistor. Also disclosed are methods of selecting a protection transistor and related components such that the bias of the protection transistor is adjusted in response to the circuit output.

Abstract: A switching circuit incorporating a high voltage transistor protection technique for use in an integrated circuit device having dual voltage supplies which extends the maximum pumped voltage (“VCCP”) for reliable MOS transistor operation to VCCP=VTN+(2*VCC), where VTN is the threshold voltage of the transistor and VCC is the supply voltage level. This is effectuated by adding an additional relatively thick gate oxide transistor in series with the relatively thin gate oxide MOS N-channel transistors in a conventional high voltage switching circuit to increase the reliable maximum voltage for the high voltage power supply.

Abstract: In a voltage generator having a voltage level detector, an oscillator, and a voltage pump, the voltage level detector comprises an amplifier, which, in combination with a first and a second linear current source, provides accurate control of an output voltage of the voltage generator. When a sensed voltage deviates around a reference voltage, a differential detection by the amplifier of this deviation causes the oscillator and the voltage pump to provide a corresponding increase or decrease in the magnitude of an output voltage in order to compensate for the deviation. Use of the amplifier and a predetermined reference voltage allows for an accurate threshold detection level for low-voltage, high-speed operation of the voltage generator. The present invention can be used in both positive and negative voltage generators.

Abstract: A CMOS transconductor that operates with increased dynamic range while maintaining one or more other basic operating characteristics at substantially the same value in comparison to a prior art transconductor circuit is provided. One embodiment, among others, comprises an input stage circuit comprising several pluralities of transistors with each plurality configured such that certain terminals of the transistors are electrically connected, and the several pluralities are electrically interconnected through one or more terminals of each plurality. Another embodiment comprises modifying an input stage of an existing transconductor circuit to provide a transconductor circuit that operates with increased dynamic range while maintaining one or more other basic operating characteristics at substantially the same value in comparison to the existing transconductor circuit.

Abstract: A timebase establishes the timing of samples acquired by a signal sampler relative to a trigger signal that is synchronous with a signal applied to the signal sampler. A first pair of samplers included in the timebase acquires samples of a reference signal and of a shifted version of the reference signal provided within the timebase, according to a synchronous trigger, to establish a first time position on the reference signal. A second pair of samplers included in the timebase acquires samples of the reference signal and the shifted reference signal according to the synchronous trigger as delayed by a programmed time interval, to establish a second time position on the reference signal. While the programmed time interval is adjusted to designate timing of the sample acquisitions by the signal sampler, the two pairs of samplers in conjunction with a timing analyzer accurately determine the timing of these sample acquisitions based on the established time positions on the reference signal.

Abstract: A method and apparatus are taught for driving a gate of a power device to turn on the power device utilizing a lossless gate driver circuit. The circuit comprises in parallel a power section, a rectifying section, a switching section, a capacitance, and an anti-spiking section. The circuit further comprises a transformer section coupled to the rectifying section, the switching section, and the anti-spiking section and a power device coupled to a portion of the anti-spiking section. The system is configured to regenerate substantially all energy utilized to power the power device via the coupling of the transformer section to the rectifying section, the switching section, the capacitance, and the anti-spike section.

Abstract: Switched-capacitor structures are provided that reduce distortion and noise in their processed signals because they increase isolation between structural elements and ensure that selected elements are securely and quickly turned off and on in different modes.

Abstract: A sense amplifier in which its output nodes provide a full voltage swing between the supply and return nodes. The sense amplifier further includes a reset circuit to selectively equalize the first and second output nodes. An output of the sense amplifier is coupled to either a digital logic gate or a flip-flop to receive the full swing. Each field effect transistor (FET) of the input pair in the sense amplifier is either zero body biased or forward body biased, so that a bulk-source junction of each FET is either zero biased or forward biased.

Abstract: An amplifier and system includes hysteresis circuits.

Abstract: A comparator network includes a comparator and a switched capacitor front end coupled to the comparator. The switched capacitor front end includes an input signal sampling capacitance, a reference signal sampling capacitance, and a switch network for coupling the input signal sampling capacitance and the reference signal sampling capacitance between a sampling configuration and a charge sharing configuration. The input signal sampling capacitance is realized with first and second differential input sampling capacitors, and the reference signal sampling capacitance is realized with first and second differential reference signal capacitors. Clocks change the switched capacitor front end between the sampling configuration and the charge sharing configuration. The comparator network is set at a preselected voltage threshold by setting a ratio of the reference sampling capacitance to the input sampling capacitance equal to a ratio of the preselected threshold voltage to a reference voltage.

Abstract: A system embodiment for controlling an electrical signal level has a first and a second switch, with one of the switches connected to a high voltage source and the other connected to a low voltage source. One of the switches is biased to an on position when the voltage is less than the low level, with the signal increasing to a level of at least the low level while the switch is biased to the on position. The other of the switches is biased to an on position when the signal is greater than the high level, with the signal discharging to at least below the high level while the switch is in the on position.

Abstract: A circuit configured to (i) receive a differential signal pair and (ii) generate one or more common mode signals. The circuit generally provides a large impedance on each input line.

Abstract: An integrated circuit device is discussed that includes an data output driver having two modes of operation for driving a data bus. The output driver includes a circuits to produce a full drive output high signal, a partial drive output high signal, a full drive output low signal and a partial drive output low signal. The output driver is protected against negative voltages on the data bus. The output driver is selectable and adaptable to drive terminated loads and unterminated loads.

Abstract: A full rail-to-rail CMOS comparator is provided. The comparator includes a gain stage and a bias stage. The bias stage is responsive to the common mode input voltage level to provide a bias signal that maintains the gain stage with an optimum operating range regardless of the level of the common mode input voltage, thus maintaining the comparator output responsive to the differential input voltage. Accordingly, when operating in the optimum operating range, duty cycle distortion of the signal at the comparator output is minimized. The comparator also offers improved performance due to a lower component count and fewer comparator stages, thus decreasing power consumption and improving propagation delays.

Abstract: In order to provide a circuit arrangement (100) for generating and amplifying a DC signal, referred to as level voltage, whose value is essentially proportional to the logarithm of the voltage amplitude of the input signal, the circuit arrangement comprising an amplifier circuit having at least two amplifier stages (10; 20; 30), it is proposed that at least a differential amplifier stage (40), in particular non-negatively fed back, is arranged parallel to the last amplifier stage (30), particularly parallel to the collector circuits of the last amplifier stage (30), the differential amplifier stage (40) precedes at least a multiplier stage (50) for multiplying the output signals of the differential amplifier stage (40), for generating two differential amplifier output signals which are to be multiplied by each other, and alternatively to the differential amplifier (40), the collector currents of the transistors (36, 38) of the rectifier circuit (35) of the last amplifier stage (30) are used, and at least a cu

Abstract: A semiconductor integrated circuit includes a plurality of logical elements connected in series or parallel, the plurality of logical elements including a semiconductor substrate and an insulating layer provided on the semiconductor substrate; and a buffer circuit connected between a logical element group including at least two of the plurality of logical elements and another logical element group including at least two of the plurality of logical elements.