Abstract: A final stage for a high-speed comparator, and a method of driving an electric load having a capacitive component are disclosed. The final stage comprises a first or pull-up component and a second or pull-down component which are connected in series with each other between a first or supply voltage reference and a second voltage reference. A dynamic drive device and a separate static drive device are coupled to each component of the output stage. Each component of the final stage is driven separately according to whether it is in a static or a dynamic load condition.

Abstract: A dynamic logic multiplexer has pull-ups on its input signals that pull-up the input signals when not selected. This reduces leakage current that may contribute to incorrect switching of the output. The output stage of the multiplexer includes a latched dynamic node followed by two gain stages, and an open-drain output.

Abstract: A deice maximizes the allowable granularity of adjustment of a bus driver line characteristics by compensating for temperature variations by selecting components that have an opposite and approximately equal thermal coefficient. In the first aspect, component parts may be made smaller because their tolerances need not be made so precise. In the second aspect, duplicating the circuitry with matching characteristics allows one circuit to be operational while the other circuit is tested or dormant. Switching between the two circuits is performed seamlessly with no interruption of device operation.

Abstract: Apparatus (1) for generating a control signal for a tunable circuit (3) sensitive to temperature receives an input control signal and predistorts it in a distortion circuit (4), so that the output (5) of the tunable circuit (3) will be substantially corrected for non-linearities in the tunable circuit (3). The distortion circuit (4) includes a linear non-distortion circuit element (9), which may be a linear temperature compensation element, and one or more non-linear distortion circuit elements (12, 13, 14), each of which distort the input control signal according to a different function. The outputs of the distortion circuit elements are passed to variable gain elements (17, 18, 19, 20) to produce weighted components. The weighted linear and non-linear components are then combined in a combination circuit element (8) to provide a predistorted control signal to the tunable circuit (3).

Abstract: A threshold amplifier receives a logic supply voltage and a ground voltage and includes a Schmitt trigger comprising an inverter stage and a hysteresis stage connected to the inverter stage for setting a high and a low hysteresis threshold. A disabling circuit disables the hysteresis stage as a function of a level of the logic supply voltage. The threshold amplifier further includes a detection circuit for detecting the level of the logic supply voltage with respect to a detection threshold, and for activating the disabling circuit for disabling the hysteresis stage when the level of the logic supply voltage is below the detection threshold.

Abstract: A DC offset cancellation circuit that is capable of canceling a DC offset voltage occurring between a pair of differential output signals of a differential amplification circuit, while preventing a signal waveform from being distorted due to accumulation of AC components and a photo-electric pulse conversion circuit that is capable of generating an electrical pulse signal that accurately reproduces a rise timing and a fall timing of an optical pulse signal by canceling the DC offset voltage are provided. A photo-electric pulse conversion circuit is provided with a photodiode, an I-V conversion circuit, a first differential amplification circuit having a DC offset cancellation circuit, a second differential amplification circuit, a reference voltage generation circuit, and a comparison circuit.

Abstract: An ESD clamping circuit arranged in a darlington configuration and constructed from SiGe or similar type material. The ESD clamping circuit includes additional level shifting circuitry in series with either the trigger or clamping device or both, thus allowing non-native voltages that exceed the BVCEO of the trigger and/or clamp devices.

Abstract: A fuse circuit configuration is described wherein a compensation capacitor counteracts a parasitic capacitor. The parasitic capacitor occurs between a connection point of a switching transistor and a fuse and ground. The compensation capacitor is connected to an evaluation circuit. In this manner, the negative effects caused by the parasitic capacitor are compensated for.

Abstract: A power voltage driver circuit includes: a constant voltage generating unit for generating a first constant voltage and a second constant voltage; a clock input buffer unit using an internal step-down voltage as a power source; a control unit for receiving an operation control signal indicating the low power operation mode; a voltage comparing unit controlled in response to the output signal from the control unit, for stopping the operation in the low power operation mode, and receiving the first and second constant voltages in the other operation modes, and generating a signal by comparing and amplifying the first and second constant voltages with a reference voltage; and a driver unit controlled in response to the output signal from the control unit.

Abstract: A new linearized transconductance circuit for converting an input into an output has been achieved. This linearized transconductance circuit is especially suited for application in a mixing circuit using a double-balanced cell. The circuit allows optimization of linearity and noise figure without excessive current. The input comprises first and second phases having a differential voltage therebetween. The output comprises first and second phases having a differential current therebetween that is proportional to the differential voltage. The circuit comprises, firstly, first, second, third, and fourth MOS transistors, with each transistor having a gate, a drain, and a source. The gates of the first and third MOS transistors are coupled to the input first phase. The drains of the first and third transistors are coupled to the output first phase. The gates of the second and fourth MOS transistors are coupled to the input second phase.

Abstract: A driver circuit 605 including a p-channel transistor 606 for driving an output from a supply rail at a positive supply voltage, p-channel transistor 606 disposed in an n-well. A detector 500 detects ramp down of the supply voltage below a preselected threshold voltage while a power reservoir 301 maintains a preselected well voltage of the n-well after the supply voltage ramps down below the preselected threshold.

Abstract: Disclosed is a circuit for driving a gate of an IGBT (insulated gate bipolar transistor) inverter. The present invention includes a first IGBT of which collector is connected to a DC voltage, a second IGBT of which collector is connected to an emitter of the first IGBT, wherein an output signal is outputted from a connection point between the collector of the second IGBT and the emitter of the first IGBT, and of which emitter is connected to a ground, first and second driving circuits supplying gates and the emitters of the first and second IGBTs with DC driving voltages, respectively, through first and second gate resistors, and first and second noise interruption circuits connected between the gates-emitters of the first and second IGBTs and the first and second driving circuits, respectively, so as to interrupt noises.

Abstract: A peak hold circuit that can operate to follow changes in peak value even if the changes are abrupt. The peak hold circuit (1) of the present invention has current control circuit (31), auxiliary switch element (25), and auxiliary constant current circuit (26). Current control circuit (31) counts the number of reference clock pulses RCK after output signal Vout becomes higher than analog voltage DI. When the number of clock pulses counted reaches a prescribed number or larger, auxiliary switch element (25) is turned on to operate auxiliary constant current circuit (26) to increase the amount of drop of output signal Vout per unit time. Consequently, even if output signal Vout becomes higher than the peak value of analog voltage DI, it is possible, by increasing the amount of drop of output signal Vout to make output signal Vout lower than analog voltage DI in a shorter amount of time than in the case in the conventional technology.

Abstract: A current mode step attenuation control circuit with digital technology. The circuit includes several stages of serially connected current attenuation circuits, each having a digital control input port, common mode feedback signal input port and bias input port, which are connected to corresponding a digital control signal, a common mode feedback current and a bias voltage, respectively. An analog input signal inputted to the circuit is controlled by the digital control signal to implement step attenuation. By using the conducting resistance of a MOS transistor to form equivalent resistance or match of current source for attenuation, the circuit eliminates dependence on resistance match of conventional technology. Because step attenuation is directly controlled by a digital control signal, the transmission speed is fast, phase delay is small, control accuracy is high and the device is suitable for digital integrated circuit manufacturing technology.

Abstract: A peak detector circuit for detecting a peak output signal including an input circuit for inputting an input signal, a comparator for comparing the input signal and said peak output signal to generate a difference signal, a current source to generate a current in response to the difference signal, and a comparator to generate the peak output signal based on said current.

Abstract: It is an object to suppress the influence of a noise pulse with a switching operation of a power switching element. A pulse generator (1) alternately outputs a pulse train having two pulses to outputs (A) and (B) synchronously with a signal input to a terminal (HIN). The pulse train is level shifted through switching elements (2) and (3) and resistive elements (8) and (9) which constitute a set of level shift circuits and is input to a flip-flop circuit (4). An output signal of the flip-flop circuit (4) is input to a control electrode of a power switching element (21) through a buffer circuit (35).

Abstract: A level-turning point of input data is detected; and a sampling clock is generated in response to the level-turning point of the input data. The input data are sampled in synchronization with the sampling clock.

Abstract: A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

Abstract: A sense amplifier adapted to sense an input signal on global bitlines, having an amplifier offset cancellation network and an offset equalization network. The amplifier offset cancellation network mitigates an inherent offset signal value, a dynamic offset signal value, or both, yet produces a residual offset signal value, which is substantially eliminated by the offset equalization network. The sense amplifier also can include an isolation circuit to isolate the sense amplifier from the corresponding global bitlines when the sense amplifier is unused. Also, a charge-sharing circuit is used to share charge between the bitlines when the sense amplifier is activated, thus producing a limited voltage swing on the bit lines. The sense amplifier uses an amplifier offset cancellation network having multiple precharge-and-balance transistors, and an offset equalization network having at least one balancing transistor.

Abstract: A hybrid power MOSFET having a low blocking-capability MOSFET and a high blocking-capability junction FET is disclosed. In accordance with the present invention, this cascode circuit has at least two high blocking-capability junction FETs which are electrically connected in parallel and whose gate connections are respectively electrically conductively connected to the source connection of the low blocking-capability MOSFET by means of a connecting line. Thus, a hybrid power MOSFET for a high current-carrying capacity is obtained whose design technology has been considerably simplified on account of the use of only one control line and n+1 chips.