Abstract: A predriver receives control information and provides an output signal for implementing control of an associated power switch device. The control information triggers a change in the output signal, such as from a first generally stable level to a second generally stable level. During the change in the output signal, the predriver operates in at least two transitional modes to control the output signal. The different transitional modes, for example, cause the output signal of the predriver to change at different rates. An associated pair of high side and low side predrivers further can be implemented in combination with a set of respective high side and low side power switches so as to form a driver.

Abstract: A differential comparator having offset correction and common mode control providing stable op amp output that changes only due to the original inputs coming into the comparator. The difference comparator has increased common-mode difference tolerance, and large op-amp offset tolerance, as well as fast decision time.

Abstract: A data receiver circuit uses two parallel differential circuits to process incoming data signals. The parallel differential circuits each compare the data signal to a different clock signal. In one embodiment, the clock signals are complementary signals. Further, the parallel differential circuits are coupled to control a current mirror circuit such that an output of the data receiver is controlled in response to a differential transition between the data signal and one of the complementary clock signals. In one embodiment, a first differential circuit includes a transistor controlled by a CLK signal and a transistor controlled by the Data signal. The second differential circuit includes a transistor controlled by a /CLK signal (complement of CLK) and a transistor controlled by the Data signal.

Abstract: A differential discrete-time signal processing channel differentially processes cardiac signals in an implantable cardiac rhythm management device. Such signal processing effectively uses downsampling to uses lower bias currents, thereby saving power and prolonging the life of the implanted device, and also reduces clock feedthrough, provides a wider dynamic range and better rejection of power supply noise. The device includes a continuous-time buffer, a decimator/averager and/or other filter and/or amplifier circuits, and an analog-to-digital converter, each configured for processing differential signals. The device also includes an operational transconductance amplifier (OTA), for the discrete-time differential signal processing. The OTA provides, among other things, an output common mode adjustment circuit and an offset compensation circuit.

Abstract: A line driver is disclosed. Generally, the structure of the line driver contains an amplifier stage that can operate at various voltage levels. The first external supply voltage is connected to a first power supply input of the amplifier stage. The line driver also includes a charge pump that generates at least a first internal supply voltage supplied to the amplifier stage. A switch control circuit is also included within the line driver to regulate the voltage output from the charge pump. Systems and methods for supplying various voltages to a load are also disclosed.

Abstract: In a level-shift circuit of the high-side section of an HVIC, a switching-on level-shift resistance member includes two resistors, and a switching-off level-shift resistance member includes two resistors. A logic filter set fetches potentials of the both end of the resistor as signals Aon and Bon, and fetches potentials of the both end of the resistor as signals Aoff and Boff. When an output period of the signals Bon and Boff is longer than that of the signals Aon and Aoff, the logic filter set does not output an abnormal signal by judging that a recoverry signal is detected.

Abstract: A circuit, and a method and computer program product for use with a switch having a field-effect transistor (FET). The method and computer program product include restricting the drain-source voltage of the FET to a predetermined range; and then switching the FET. In general, in one aspect, the invention features a circuit having source, drain and gate terminals. The circuit includes a first FET having a first drain coupled to the drain terminal and a first source coupled to the source terminal; a second FET having a second drain coupled to the drain terminal and a second source coupled to the source terminal; and a control circuit coupled to the gate terminal, the first gate, and the second gate.

Abstract: A method and a device for controlling an electrical load. A quantity is ascertained which is a function of the temperature of the load or which characterizes the temperature of the load. The quantity is specifiable on the basis of a temperature variable and a current variable. A first filter takes into account the influence of the temperature variable on the quantity, and a second filter takes into account the influence of the current flowing through the load.

Abstract: The opamp with a slew rate booster includes a first high side transistor 23 coupled to a first differential output node OUT−; a second high side transistor 26 coupled to a second differential output node OUT+; a first booster circuit 72 coupled to the control node of the first high side transistor 23; a second booster circuit 70 coupled to the control node of the second high side transistor 26. The opamp exploits the gate control available on the high side transistors 23 and 26. During the charge-discharge differential transient of the load capacitances 58 and 60, the circuit increases the current given by the high side transistor 23 or 26 that is pulling up its output OUT− or OUT+, and reduces by the same amount the current provided at the other output OUT+ or OUT− that is being pulled down by a low side driver 43 or 40. The gate control is accomplished through a simple, symmetrical capacitor-resistor network that implements a basic differentiator.

Abstract: An output buffer circuit (300) having an output time which may be reduced is provided. The output buffer circuit (300) can include a selector (1), a precharge circuit (2) and a buffer (3). Selector (1) can be responsive to a control signal (SELB) and may provide data on a data signal line (9). Precharge circuit (2) may be responsive to control signal (SELB) and may precharge data signal line (9) to a first potential when control signal is in a disable state. Selector (1) may electrically disconnect data input terminals (4 and 5) from data signal line (9) when control signal (SELB) is in the disable state. Buffer (3) may output a logic value from the data signal line (9) when control signal (SELB) is in an enable state.

Abstract: The present invention implements a signal processing function without the use of a DSP (digital signal processor) or ADC. A reference signal is produced that relates to a DAC output code. The reference signal is used as a starting point, and is compared to the input signal. A feedback signal is produced that is used to adjust the reference. The invention can be used to implement signal processing functions such as peak detection, noise filtering, peak suppression, and the like. The invention can implement these functions with a minimal complexity and a minimal die area.

Abstract: An apparatus to provide a novel bi-voltage level switching. The apparatus includes a first level shifting buffer coupled to a voltage supply, an input, and a first transistor. The first transistor coupled to the voltage supply and an output. A second level shifting buffer coupled to the voltage supply, the input and second transistor. The second transistor coupled to the output and a voltage source.

Abstract: A voltage buffer includes a high impedance input and a low impedance output. In one example, the buffer includes a source-follower FET and load FET, at least one of which has a forward-biased source-body junction. Another example includes a cascade of two source-follower FETs of opposite conductivity types, and corresponding load devices. Another example further reduces the buffer's output impedance by using a diode-connected load device. The voltage buffer is effectively referenced to a first power supply and effectively isolated from a second power supply. Therefore, it tracks variations in the first power supply voltage, but does not track variations in the second power supply voltage.

Abstract: The circuit has a push-pull end stage which acts as an amplifier stage for digital signals. The push-pull end stage has two n-channel MOS transistors which function as source followers and two p-channel MOS transistors which also function as source followers. The gate terminals of the respective n-channel MOS transistors and p-channel MOS transistors are each controlled by an operational amplifier through drivers. A voltage that determines the setpoint value of the high level of the output of the push-pull end stage is present at the non-inverting input of one operational amplifier and a voltage that determines the low level of the output of the push-pull end stage is present at the inverting input of the other operational amplifier.

Abstract: A control circuit for a power MOSFET includes a voltage divider for dividing an input voltage, a fixed voltage generator for generating a fixed voltage, a comparator having a differential pair including first and second depletion transistors each receiving the divided voltage or the fixed voltage and a current mirror including first and second enhancement transistors connected in series with the first and second depletion transistors, respectively, an inverter for receiving the output from the comparator, and a power MOSFET controlled for the ON/OFF control thereof by the inverter.

Abstract: A multichip configuration in which a plurality of semiconductor chips in a module are connected together in such a way that the voltage drop across internal gate resistors is minimized, in order in the event of a short circuit to prevent the short circuit current rising with the gate voltage.

Abstract: A flip-flop circuit comprises a master latch circuit (2), which receives an input signal (D), and, connected in series therewith, a slave latch circuit (3), the two latch circuits (2, 3) being actuated complementarily-to one another by a clock signal. The output signal value (Q,{overscore (Q)}) of the flip-flop circuit is emitted from the output of the slave latch circuit (3) not directly but via a non-differential output driver circuit (4), e.g. an inverter circuit.

Abstract: A hardware-based random number generator is provided for incorporation within an integrated circuit. The apparatus has a first variable frequency oscillator, a second variable frequency oscillator, and a variable bias generator. The first variable frequency oscillator generates a first oscillatory signal at a first frequency. The a second variable frequency oscillator generates a second oscillatory signal that is asynchronous to the first oscillatory signal and has a second frequency less than the first frequency, where bits of the random number are configured from samples of the first oscillatory signal taken at the second frequency. The variable bias generator is coupled to the first and second variable frequency oscillators, and generates an analog bias signal. The first and second frequencies vary according to the analog bias signal, and the analog bias signal varies based upon logic states of a plurality of bits of the random number.

Abstract: One embodiment of the present invention provides resistor within an integrated circuit with a substantially linear resistance. This resistor includes a diode-connected transistor coupled in parallel with a current-source-connected transistor, so that a nonlinear resistance of the diode-connected transistor combines with a nonlinear resistance of the current-source-connected transistor to produce a substantially linear combined resistance. It also includes selection circuit that is configured to selectively deactivate the resistor by deactivating the diode-connected transistor and the current-source-connected transistor. This selection circuit provides a range of possible resistance values, and thus enables the resistance to be quickly switched on and off to allow for use in a high-speed driver circuit.

Abstract: An input receiver capable of sensing and amplifying an external signal having a very small swing input signal. The input receiver comprises a clock sampled amplifier for receiving a clock signal and a reference signal, respectively, in response to a first state of a clock signal and a delayed sampling clock signal, and for amplifying and sampling the voltage difference between the external signal and the reference signal, respectively, in response to a transition of the clock and delayed sampling clock signals to a second state; and a pulse generator for pre-charging a power source voltage and selectively pulling down the pre-charged signals to produce a pulse signal, in response to the second state of the delayed sampling clock signal and outputs of the clock sampled amplifier.