Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are stacked in a vertical direction. Each channel extends in a first direction. The gate structure extends in a second direction. The gate structure covers the channels. The source/drain layer is connected to each of opposite sidewalls in the first direction of the channels on the substrate, and includes a doped semiconductor material. The source/drain layer includes first and second epitaxial layers having first and second impurity concentrations, respectively. The first epitaxial layer covers a lower surface and opposite sidewalls in the first direction of the second epitaxial layer. A portion of each of opposite sidewalls in the first direction of the gate structure protrudes in the first direction from opposite sidewalls in the first direction of the channels to partially penetrate through the first epitaxial layer but not to contact the second epitaxial layer.

Abstract: An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first transistor is formed on a substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions. A top surface of the first vertical portion in and a top surface of one of the first horizontal portions are coplanar.

Abstract: A transistor includes a first gate structure, a channel layer, and source/drain contacts. The first gate structure includes metallic nanosheets. Each of the metallic nanosheets includes a top surface, a bottom surface opposite to the top surface, and sidewalls connecting the top surface and the bottom surface. The channel layer surrounds the top surfaces, the bottom surfaces, and the sidewalls of the metallic nanosheets. The source/drain contacts are electrically connected to the channel layer. A portion of the channel layer is located between the source/drain contacts and the metallic nanosheets.

Abstract: An electronic device includes an interconnect layer, a second chip and a third chip provided on a first side of the interconnect layer, and a first chip provided on a second side of the interconnect layer. The interconnect layer includes conductive members connecting between the first chip and the second chip, and connecting between the first chip and the third chip, respectively. The interconnect layer does not include a conductive member directly connecting between the second chip and the third chip.

Abstract: A display panel and a display apparatus are provided. The display panel includes a substrate, binding pins provided at a side of the substrate, and insulating layers. The substrate has a display region and a binding region that are arranged along a first direction. The binding pins are arranged along a second direction and are located in the binding region of the substrate. The insulating layers and the binding pins are arranged on a same side of the substrate. At least one insulating layer includes at least one first aperture provided at a side of the binding region away from the display region. An orthographic projection of the first aperture on the substrate overlaps with an orthographic projection of the binding pin on the substrate in the first direction.

Abstract: The disclosure concerns a device which comprises a stack of two high electron mobility transistors, referred to as first and second transistor, separated by an insulating layer and each provided with a stack of semiconductor layers respectively referred to as first stack and second stack, the first and the second stack each comprising, from the insulating layer to, respectively, a first and a second surface, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first set of electrodes and a second set of electrodes, the first and the second set of electrodes each comprising a source electrode, a drain electrode, and a gate electrode which are arranged so that the first and the second transistor are electrically connected head-to-tail.

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.

Abstract: An integrated circuit includes first-type transistors aligned within a first-type active zone, second-type transistors aligned within a second-type active zone, a first power rail and a second power rail extending in a first direction. A first distance between the long edge of the first power rail and the first alignment boundary of the first-type active zone is different from a second distance between the long edge of the second power rail and the first alignment boundary of the second-type active zone. Each of the first distance and the second distance is along a second direction which is perpendicular to the first direction.

Abstract: A display panel and a display apparatus are provided. The display panel includes a base substrate including a pixel circuit and a light-emitting element. The pixel circuit includes a data writing sub-circuit, a storage sub-circuit, a driver sub-circuit and a first sub-circuit. The data writing sub-circuit is configured to transmit a data signal to a first terminal of the storage sub-circuit in response to a control signal. A control electrode of the driver sub-circuit is coupled to the storage sub-circuit, a first electrode of the driver sub-circuit is configured to receive a first power supply voltage, and a second electrode is coupled to a first electrode of the light-emitting element. The first sub-circuit includes a first transistor, where a gate and a first electrode of the first transistor are both coupled to the same electrode of the driver sub-circuit.

Abstract: A memory circuit includes first and second read-only memory (ROM) cells aligned along a first active structure including a first shared source portion of the first and second ROM cells, third and fourth ROM cells aligned along a second active structure including a second shared source portion of the third and fourth ROM cells, a first bit line overlying the first and second ROM cells, a second bit line overlying the third and fourth ROM cells, and a reference voltage line positioned between the first and second bit lines and in a same metal layer as the first and second bit lines. A conductive structure is electrically connected to each of the first and second shared source portions and the reference voltage line and is positioned in a metal layer below the same metal layer.

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration.

Abstract: Methods for depositing a molybdenum nitride film on a surface of a substrate are disclosed. The methods may include: providing a substrate into a reaction chamber; and depositing a molybdenum nitride film directly on the surface of the substrate by performing one or more unit deposition cycles of cyclical deposition process, wherein a unit deposition cycle may include, contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, and contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor. Semiconductor device structures including a molybdenum nitride film are also disclosed.

Abstract: A light-emitting element includes: a first electrode serving as an anode; a second electrode serving as a cathode; a light-emitting layer, of a first wavelength range, provided between the first electrode and the second electrode; an oxide layer provided between the light-emitting layer of the first wavelength range and the first electrode of the first electrode and the second electrode; and an oxide layer provided between the oxide layer and the second electrode, and having contact with the oxide layer. Either the oxide layer or the oxide layer whichever farther away from the light-emitting layer of the first wavelength range is made of a semiconductor. A density of oxygen atoms in the oxide layer is lower than a density of oxygen atoms in the oxide layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

Abstract: A super-steep switching device is provided. The super-steep switching device may include a substrate, a semiconductor channel on the substrate, a source electrode and a drain electrode, which are disposed on the semiconductor channel and spaced apart from each other, a gate electrode overlapping a portion of the semiconductor channel and not overlapping a remaining portion of the semiconductor channel, and an insulating layer disposed between the gate electrode and the semiconductor channel and covering an entire surface of the semiconductor channel.

Abstract: A display panel including: a display region including pixels and a non-display region, each pixel including an emission element including a first electrode, an emission layer, and a second electrode; a pixel definition layer including a first opening; a first encapsulation layer on the pixel definition layer and overlapping the emission element; a partition wall on the first encapsulation layer and including a second opening and a dummy opening; a light control pattern in the second opening; a second encapsulation layer on the partition wall and overlapping the light control pattern; and a color filter on the second encapsulation layer and overlapping the light control pattern, the second encapsulation layer includes: a first encapsulation inorganic layer on the partition wall; an encapsulation organic layer on the first encapsulation inorganic layer and including an edge overlapping the dummy opening; and a second encapsulation inorganic layer on the encapsulation organic layer.

Abstract: A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.