Patents Examined by Tong-Ho Kim
  • Patent number: 10811520
    Abstract: A method for manufacturing a semiconductor device, includes: forming a well region (201) in a semiconductor substrate (200) and forming a channel region (202) in the well region (201), and forming a gate oxide layer (210) and a polysilicon layer (220) on the well region (201); etching a portion of the gate oxide layer (210) and the polysilicon layer (220), and exposing a first opening (221) used for forming a source region and a second opening (223) used for forming a drain region; forming a first dielectric layer (230) and a second dielectric layer (240) on the polysilicon layer (220) and in the first opening (221) and the second opening (223) successively, and forming a source region side wall at a side surface of the first opening (221) and forming a drain region side wall at a side surface of the second opening (223); forming a dielectric oxide layer (250) on the polysilicon layer (220), etching the dielectric oxide layer and retaining the dielectric oxide layer (250) located on the drain region side wall
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: October 20, 2020
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Huajun Jin, Guipeng Sun
  • Patent number: 10811339
    Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In which a uniform metal layer is formed above the second metal layer of the second wafer, the uniform metal layer is electrically connected to the second metal layer, and the uniform metal layer and the first metal layer are made of the same material. The uniform metal layer and the first metal layer simultaneously exposed by the subsequently formed TSV hole are made of the same material, the degree of over-etching is relatively easy to control in the etching process, and cross contamination of cleaning agents in the cleaning process can be avoided. In addition, when the interconnection layer is electrically connected to the first metal layer and the uniform metal layer, since the uniform metal layer and the first metal layer are made of the same material, the interconnection layer has better contact performance with the two.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: October 20, 2020
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tian Zeng
  • Patent number: 10804478
    Abstract: Provided are a foldable display panel, a manufacturing method thereof and a foldable display device. The foldable display panel is improved by replacing the conventional inorganic insulating layer with a bending resistant organic insulating layer to improve the bendability of the display panel; meanwhile, the cross-interconnected metal foil layer is added between the organic insulating layers to improve the resilience after bending, thereby improving the reliability of the product while improving the bending resistance of the display panel.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: October 13, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Hong Fang
  • Patent number: 10800967
    Abstract: Provided is a ceramic composition capable of achieving a light scattering function while maintaining optical properties at a high level. The ceramic composition comprises a fluorescence phase comprising a fluorescent material and a light-scattering phase comprising a lanthanum oxide. The lanthanum oxide may be, for example, at least one selected from LaAlO3 and La2O3. The ratio of the fluorescent material (or the fluorescence phase) to the lanthanum oxide (or the light-scattering phase), the former/the latter, may be 99.9/0.1 to 50/50 in terms of volume ratio.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: October 13, 2020
    Assignee: Konoshima Chemical Co., Ltd.
    Inventors: Takagimi Yanagitani, Katsuhiro Muramatsu, Atsuko Endo, Kazunari Shiota
  • Patent number: 10797120
    Abstract: In an embodiment, an array substrate includes a substrate having a display region and a package region surrounding the display region, wherein the display region comprises a side region adjacent to the package region; a pixel definition layer disposed on the display region of the substrate, wherein the pixel definition layer is formed with a plurality of recesses and a plurality of corresponding protrusions surrounding each recess, and each recess and each protrusion correspond to the side region; and a cathode trace disposed on a surface of each protrusion and a bottom surface of each recess, wherein a gap exists between the cathode trace on each protrusion and the cathode trace in each recess.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: October 6, 2020
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Xingyong Zhang
  • Patent number: 10790317
    Abstract: A flexible display device is provided. The flexible display device comprises a flexible substrate on which an active layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer, a second metal layer, a planar layer, an emitting layer and an encapsulation layer are sequentially stacked. The gate insulating layer covers the active layer, the interlayer insulating layer covers the gate metal layer and the planar layer covers the interlayer insulating layer and the second metal layer. A plurality of channels is disposed on the interlayer insulating layer, and both two ends of the channels extending toward edge of the interlayer insulating layer to penetrate the interlayer insulating layer.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: September 29, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Wei Wang
  • Patent number: 10790142
    Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chien Chi, Hsiao-Kuan Wei, Hung-Wen Su, Pei-Hsuan Lee, Hsin-Yun Hsu, Jui-Fen Chien
  • Patent number: 10790414
    Abstract: A light emitting diode includes an N-type semiconductor layer, a P-type semiconductor layer, and a light emitting layer. The P-type semiconductor layer is located on the N-type semiconductor layer. The light emitting layer is located between the N-type semiconductor layer and the P-type semiconductor layer. The N-type semiconductor layer has a first region and a second region connected to each other. The first region is overlapped with the light emitting layer and the P-type semiconductor layer in a first direction. The second region is not overlapped with the light emitting layer and the P-type semiconductor layer in the first direction. A sheet resistance of the P-type semiconductor layer is smaller than a sheet resistance of the N-type semiconductor layer.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: September 29, 2020
    Assignee: Au Optronics Corporation
    Inventors: Pu-Jung Huang, Pin-Miao Liu, Cheng-Yeh Tsai, Chen-Chi Lin
  • Patent number: 10790397
    Abstract: A gate electrode (6) is provided on the semiconductor layer (2) and a least includes a lowermost layer (6a) in contact with the semiconductor layer (2), and an upper layer (6b) provided on the lowermost layer (6a). The upper layer (6b) applies stress to the lowermost layer (6a) to cause both edges of the lowermost layer (6a) to curl up from the semiconductor layer (2).
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 29, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tasuku Sumino, Takayuki Hisaka
  • Patent number: 10790249
    Abstract: The invention concerns a discrete electronic component including: a semiconductor chip including a transistor, the chip including a first metallization of connection to a first conduction region of the transistor; and a printed circuit board including first and second separate connection pads, wherein: the chip is assembled on the printed circuit board so that the first metallization of the chip is in contact with the first and second connection pads of the printed circuit board; and the assembly including the semiconductor chip and the printed circuit board is encapsulated in a package made of an insulating material leaving access to first and second connection terminals of the component connected, inside of the package, respectively to the first and second connection pads of the printed circuit board.
    Type: Grant
    Filed: June 23, 2019
    Date of Patent: September 29, 2020
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sébastien Carcouet, Xavier Maynard
  • Patent number: 10790282
    Abstract: A semiconductor device may include active fins spaced apart from each other by a recess therebetween, each of the active fins protruding from an upper surface of a substrate, an isolation structure including a liner on a lower surface and a sidewall of a lower portion of the recess and a blocking pattern on the liner, the blocking pattern filling a remaining portion of the lower portion of the recess and including a nitride, a carbide or polysilicon, a gate electrode structure on the active fins and the isolation structure, and a source/drain layer on a portion of each of the active fins adjacent to the gate electrode structure.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-Jung Choi, Dong-Hyun Roh, Sung-Soo Kim, Gyu-Hwan Ahn, Sang-Jin Hyun
  • Patent number: 10784259
    Abstract: Provided is a semiconductor device including a substrate, an isolation structure, a barrier structure, a first conductive layer, a second conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The substrate has a first region and a second region. The barrier structure is located on the isolation structure. The first conductive layer is located on the first region. The second conductive layer is located on the second region. The first gate dielectric layer is located between the first conductive layer and the substrate in the first region. The second gate dielectric layer is located between the second conductive layer and the substrate in the second region. The first gate dielectric layer and the second gate dielectric layer are separated by the isolation structure. A method of manufacturing the semiconductor device is also provided.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: September 22, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Hung-Kwei Liao, Chen-Chiang Liu, Kuo-Sheng Shih, Yung-Yao Shih, Ming-Tsung Hsu
  • Patent number: 10784298
    Abstract: Embodiments of the present application, pertaining to the technical field of optical devices, provide an optical module and a fabrication method thereof, and a terminal device using the same. The optical module includes a lens and a sensor package. The lens is positioned at an uppermost position of the optical module and attached to a lower position of a terminal screen, and is configured to transmit light passing through the screen; the sensor package includes an optical sensor, where a photosensitive region is arranged on an upper surface of the optical sensor, and the photosensitive region is configured to receive light passing through the lens; and the sensor package further includes an air gap, and the photosensitive region of the optical sensor is configured to receive the light passing through the screen via the air gap.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: September 22, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Haoxiang Dong, Ya Wei, Wei Long, Baoquan Wu
  • Patent number: 10777683
    Abstract: A thin film transistor, a method of manufacturing the same, an array substrate and a display panel are disclosed. The thin film transistor includes a light blocking layer, an electrode layer, and a combination layer, which are sequentially stacked. The electrode layer includes a gate electrode, a source electrode and a drain electrode which are separated from one another, and the gate electrode is located between the source electrode and the drain electrode. The light blocking layer includes a first portion of which an orthogonal projection is located between an orthogonal projection of the gate electrode and an orthogonal projection of the source electrode; and a second portion of which an orthogonal projection is located between the orthogonal projection of the gate and an orthogonal projection of the drain. The combination layer includes an active layer.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 15, 2020
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yang Zhang, Luke Ding, Bin Zhou, Haitao Wang, Ning Liu, Jingang Fang, Yongchao Huang, Liangchen Yan
  • Patent number: 10777576
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Byeung Chul Kim, Francois H. Fabreguette, Richard J. Hill, Purnima Narayanan, Shyam Surthi
  • Patent number: 10777708
    Abstract: An optoelectronic semiconductor chip includes a semiconductor layer sequence, a transparent substrate, at least one contact trench, at least one insulating trench, at least one current distribution trench, at least in the insulating trench, an electrically insulating mirror layer that reflects radiation generated in an active layer, at least one metallic current web in the contact trench configured for a current conduction along the contact trench and supplying current to a first semiconductor region, and at least one metallic busbar in the current distribution trench that energizes a second semiconductor region, wherein the contact trench, the isolating trench and the current distribution trench extend from a side of the second semiconductor region facing away from the substrate through the active layer into the first semiconductor region, and the contact trench is completely surrounded by the insulating trench, and the current distribution trench lies only outside the insulating trench.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: September 15, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Fabian Kopp, Attila Molnar
  • Patent number: 10777594
    Abstract: In a global shutter system back-illuminated CMOS image sensor, optical noise is reduced to enhance image quality. A solid-state imaging element is provided that includes: a semiconductor substrate; a photoelectric conversion unit; a charge holding unit; a first penetrating light-shielding film that partitions the photoelectric conversion unit and the charge holding unit from each other; a first bypass part containing a semiconductor material on an outer front surface of the semiconductor substrate; and a control unit that controls charge transfer from the photoelectric conversion unit to the charge holding unit via the first bypass part. A front-side end portion of the first penetrating light-shielding film has, in a thickness direction of the semiconductor substrate, an approximately same length as a front-side end of the charge holding unit or has a longer length than in the front-side end of the charge holding unit in a front side direction.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: September 15, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Shinichi Arakawa
  • Patent number: 10777494
    Abstract: We disclose herein a semiconductor device sub-assembly comprising: a plurality of semiconductor units laterally spaced to one another; a plurality of conductive blocks, wherein each conductive block is operatively coupled with each semiconductor unit; a conductive malleable layer operatively coupled with each conductive block, wherein the plurality of conductive blocks are located between the conductive malleable layer and the plurality of semiconductor units. In use, at least some of the plurality of conductive blocks are configured to apply a pressure on the conductive malleable layer, when a predetermined pressure is applied to the semiconductor device sub-assembly.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: September 15, 2020
    Assignees: DYNEX SEMICONDUCTOR LIMITED, ZHUZHOU CRRC TIMES ELECTRONIC CO. LTD.
    Inventor: Robin Adam Simpson
  • Patent number: 10770684
    Abstract: A display device includes a substrate having a first area, a second area, and a bending area between the first area and the second area. A display element is disposed in the first area of the substrate. A stress neutralizing layer is disposed in the first area, the second area and the bending area. A thickness of the stress neutralizing layer in the bending area is less than a thickness of the stress neutralizing layer in at least one of the first area or the second area.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kwangho Lee, Jaeyoung Sim, Kyungho Jung
  • Patent number: 10770288
    Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu