Patents Examined by Tong-Ho Kim
  • Patent number: 11152514
    Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 19, 2021
    Assignee: INTEL Corporation
    Inventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
  • Patent number: 11152291
    Abstract: A multilayer substrate includes a plurality of plates laminated in a thickness direction of the multilayer substrate, a resin layer provided between the plurality of plates adjacent in the thickness direction, an internal conductive layer provided between the plurality of plates adjacent in the thickness direction, and an external conductive layer provided over an outer surface of each plate of the plurality of plates located at both ends in the thickness direction, wherein a total thickness of the internal conductive layer and the external conductive layer is equal to or less than 25% of a total thickness of the plurality of plates.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 19, 2021
    Assignee: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
    Inventors: Toshiki Iwai, Taiji Sakai
  • Patent number: 11152403
    Abstract: This application provides a method for manufacturing an array substrate, an array substrate, and a display panel. A gate metal layer, a gate insulating layer, and a semiconductor active layer are formed by using one photomask process, a first passivation layer is formed in one photomask process, and a source metal layer, a drain metal layer, and a pixel electrode layer are formed on the first passivation layer.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: October 19, 2021
    Assignees: CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD., HKC CORPORATION LIMITED
    Inventors: Fengyun Yang, En-Tsung Cho
  • Patent number: 11152261
    Abstract: Techniques for self-aligned top via formation at line ends are provided. In one aspect, a method of forming self-aligned vias at line ends includes: patterning (even/odd) metal lines including using a (first/second) hardmask; cutting the hardmask and a select metal line, even or odd, using a cut mask having a window that exposes the hardmask over a cut region of the select metal line; enlarging the window to expose the hardmask on either side of the cut region; selectively etching the hardmask using the enlarged window to form a T-shaped cavity within the cut region; filling the T-shaped cavity with a gap fill dielectric; removing the hardmask; and recessing the metal lines, wherein the gap fill dielectric overhangs portions of the select metal line that, by the recessing, form the self-aligned vias at ends of the metal lines. A structure is also provided.
    Type: Grant
    Filed: October 26, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, John Arnold, Dominik Metzler
  • Patent number: 11145716
    Abstract: A structure comprises a substrate and a first gate structure and a second gate structure in a dielectric layer over the substrate. The first and second gate structures having a width, the width of the first gate structure is shorter than the width of the second gate structure. The first gate structure comprises a first gate conductor layer and the second gate structure comprises a second gate conductor layer. The first gate conductor layer is made of a different metal from the second gate conductor layer.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: October 12, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Rinus Tek Po Lee, Jiehui Shu
  • Patent number: 11145740
    Abstract: A ferroelectric field effect transistor (FeFET) device includes a semiconductor substrate and a 3D transistor. The 3D transistor includes drain and source electrodes; a channel structure that includes a channel body and a gate dielectric layer; and a gate electrode that is disposed on the gate dielectric layer and that is electrically isolated from the drain and source electrodes. The channel body is disposed between and connected to the drain and source electrodes. The gate dielectric layer covers the channel body, is made of crystalline hafnium zirconium oxide, and has a thickness ranging from 2 nm to 5 nm. The FeFET device has an on/off current ratio that is greater than 5×104.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: October 12, 2021
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Yung-Chun Wu, Fu-Ju Hou, Meng-Ju Tsai
  • Patent number: 11145753
    Abstract: The present disclosure discloses a ballistic transport semiconductor device based on nano array and a manufacturing method thereof. The ballistic transport semiconductor device based on nano array comprises a conducting substrate, more than one semiconductor nano bump portion is arranged on a first surface of the conducting substrate, a top end of the semiconductor nano bump portion is electrically connected with a first electrode, a second surface of the conducting substrate is electrically connected with a second electrode, the second surface and the first surface are arranged back to back, and the height of the semiconductor nano bump portion is less than or equal to a mean free path of a carrier. The carrier is not influenced by various scattering mechanisms in a transporting procedure by virtue of the existence of ballistic transport characteristics, thereby obtaining a semiconductor device having advantages of lower on resistance, less working power consumption.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: October 12, 2021
    Assignee: SUZHOU INSTITUTE OF NANO-TECH AND NANO-BIONICS (SINANO), CHINESE ACADEMY OF SCIENCES
    Inventors: Guohao Yu, Fu Chen, Wenxin Tang, Xiaodong Zhang, Yong Cai, Baoshun Zhang
  • Patent number: 11147197
    Abstract: Embodiments may relate to a material to provide electrostatic discharge (ESD) protection in an electrical device. The material may include first and second electrically-conductive carbon allotropes. The material may further include an electrically-conductive polymer that is chemically bonded to the first and second electrically-conductive carbon allotropes such that an electrical signal may pass between the first and second electrically-conductive carbon allotropes. Other embodiments may be described or claimed.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Veronica Aleman Strong, Johanna M. Swan, Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid
  • Patent number: 11145746
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, and forming a sacrificial film over the first semiconductor layer and the second semiconductor layer. The sacrificial film fills an area between the first semiconductor layer and the second semiconductor layer. The method further includes forming a space in the sacrificial film between the first semiconductor layer and the second semiconductor layer and removing the sacrificial film.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co.y, Ltd.
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Chi On Chui
  • Patent number: 11133367
    Abstract: A thin film transistor includes: a substrate base; a first gate electrode at a side of the substrate base; an active layer at a side of the first gate electrode away from the substrate base; a second gate electrode at a side of the active layer away from the substrate base; and a source/drain electrode at a side of the second gate electrode away from the substrate base. An orthographic projection of the source/drain electrode on the substrate base is at least partially overlapped with an orthographic projection of the second gate electrode on the substrate base.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 28, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ling Wang, Yicheng Lin, Cuili Gai, Pan Xu
  • Patent number: 11133420
    Abstract: A semiconductor device with high on-state current is provided.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 28, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Iida, Ryota Hodo, Kentaro Sugaya, Ryu Komatsu, Toshiya Endo, Shunpei Yamazaki
  • Patent number: 11127820
    Abstract: A quantum well field-effect transistor (QWFET) includes a barrier layer, a quantum well layer, and a spacer layer. The quantum well layer is on the barrier layer. The barrier layer and the spacer layer comprise aluminum indium antimonide that is undoped. The quantum well layer comprises indium antimonide. The spacer layer is on the quantum well layer. The quantum well layer and the spacer layer are between a source contact and a drain contact. A gate contact is on a dielectric layer, which is on the spacer layer. By providing the barrier layer and the spacer layer as undoped layers, a performance of the QWFET may be improved.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: September 21, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Michael James Manfra, Candice Fanny Thomas
  • Patent number: 11127831
    Abstract: Embodiments of the disclosure provide a transistor structure and methods to form the same. The transistor structure may include an active semiconductor region with a channel region between a first source/drain (S/D) region and a second S/D region. A polysilicon gate structure is above the channel region of the active semiconductor region. An overlying gate is positioned on the polysilicon gate structure. A horizontal width of the overlying gate is greater than a horizontal width of the polysilicon gate structure. The transistor structure includes a gate contact to the overlying gate.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: September 21, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Qizhi Liu, Vibhor Jain, John J. Pekarik, Judson R. Holt
  • Patent number: 11121138
    Abstract: A semiconductor device includes a transistor and a memory pickup cell formed over a well in a substrate. The transistor includes a first fin having a first width and two first source/drain features on the first fin. The pickup cell includes a second fin having a second width and two second source/drain features on the second fin. The well, the first fin, the second fin, and the second source/drain feature are of a first conductivity type. The first source/drain features are of a second conductivity type opposite to the first conductivity type. The second width is at least three times of the first width. The pickup cell further includes a stack of semiconductor layers over the second fin and connecting the two second source/drain features.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsun Chiu, Cheng-Chi Chuang, Shang-Wen Chang
  • Patent number: 11121041
    Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zoe Chen, Ching-Hwanq Su, Cheng-Lung Hung, Cheng-Yen Tsai, Da-Yuan Lee, Hsin-Yi Lee, Weng Chang, Wei-Chin Lee
  • Patent number: 11121348
    Abstract: Provided is a display. A rotary polarized light emitting device includes: a first electrode; a second electrode; a light exiting layer, first light having a polarization state in which the first light rotates in a first direction, and exit, toward the second electrode, second light having a polarization state in which the second light rotates in a second direction that is opposite to the first direction.
    Type: Grant
    Filed: November 23, 2019
    Date of Patent: September 14, 2021
    Assignee: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Jae-Hoon Kim, You-Jin Lee, Chang-Jae Yu
  • Patent number: 11121180
    Abstract: An example three-dimensional (3-D) memory array includes a substrate material including a plurality of conductive contacts arranged in a staggered pattern and a plurality of planes of a conductive material separated from one another by a first insulation material formed on the substrate material. Each of the plurality of planes of the conductive material includes a plurality of recesses formed therein. A second insulation material is formed in a serpentine shape through the insulation material and the conductive material. A plurality of conductive pillars are arranged to extend substantially perpendicular to the plurality of planes of the conductive material and the substrate and each respective conductive pillar is coupled to a different respective one of the conductive contacts. A chalcogenide material is formed in the plurality of recesses such that the chalcogenide material in each respective recess is formed partially around one of the plurality of conductive pillars.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Lorenzo Fratin
  • Patent number: 11121243
    Abstract: Disclosed is a 2D-3D HJ-TFET made of a material, the band gap of which changes according to the thickness, such as black phosphorous or TMDC, in order to extend Moore's law. More particularly, disclosed are the structure of a 2D-3D HJ-TFET and a method for manufacturing the same, wherein the 2D-3D HJ-TFET is made of a material such as black phosphorous or TMDC such that the same consumes less power, has a high switching speed, can operate in a complementary manner so as to replace a conventional CMOS transistor, and can extend Moore's law.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: September 14, 2021
    Assignee: Korea Advanced Institute of Science and Technology
    Inventor: Sungjae Cho
  • Patent number: 11107736
    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration. The method further includes depositing a work function metal layer on the high-K dielectric layer and depositing a metal fill layer on the work function metal layer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: August 31, 2021
    Inventors: Chun-Fai Cheng, Chang-Miao Liu, Kuan-Chung Chen
  • Patent number: 11107805
    Abstract: An integrated circuit includes a first cell and a second cell. The first cell with a first cell height along a first direction includes a first active region and a second active region that extend in a second direction different from the first direction. The first active region overlaps the second active region in a layout view. The second cell with a second cell height includes a first plurality of active regions and a second plurality of active regions. The first plurality of active regions and the second plurality of active regions extend in the second direction and the first plurality of active regions overlap the second plurality of active regions, respectively, in the layout view. The first cell abuts the second cell, and the first active region is aligned with one of the first plurality of active regions in the layout view.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Sing Li, Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien