Abstract: Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.

Abstract: A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.

Abstract: A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer. The semiconductor layer, the second insulating layer, and the first conductive layer are stacked in this order over the first insulating layer. The first insulating layer has a stacked-layer structure in which a first insulating film, a second insulating film, and a third insulating film are stacked in this order. The second insulating layer includes an oxide. The third insulating film includes a part in contact with the semiconductor layer. The first insulating film includes silicon and nitrogen. The second insulating film includes silicon, nitrogen, and oxygen. The third insulating film includes silicon and oxygen. The semiconductor layer includes indium and oxygen.

Abstract: A surface-mountable component is disclosed. The surface-mountable component may include a substrate having a side surface and a top surface that is perpendicular to the side surface. The component may include an element layer formed on the top surface of the substrate. The element layer may include a thin-film element and a contact pad electrically connected with the thin-film element. The contact pad may extend to the side surface of the substrate. The component may include a terminal that is electrically connected with the contact pad at a connection area. The connection area may be parallel with the top surface of the substrate. The terminal may have a visible edge surface that is approximately aligned with the side surface of the substrate. The visible edge surface may be visible for inspection when the surface-mountable component is mounted to a mounting surface.

Abstract: A semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions, where the nanosheets comprise a first semiconductor material; inner spacers between the nanosheets and at opposite ends of the nanosheets, where there is an air gap between each of the inner spacers and a respective source/drain region of the source/drain regions; and a gate structure over the fin and between the source/drain regions.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

Abstract: According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.

Abstract: A semiconductor device includes a channel layer, source/drain contacts, and first barrier liners. The channel layer includes an oxide semiconductor material. The source/drain contacts are disposed in electrical contact with the channel layer. The first barrier liners surround the source/drain contacts, respectively, and include a hydrogen barrier material so as to prevent hydrogen from diffusion through the first barrier liners to the channel layer.

Abstract: The embodiments of the present invention provide a thin film transistor (TFT) device, a manufacturing method thereof, and an array substrate. A gate electrode comprises a first sub-gate electrode and a second sub-gate electrode disposed on different layers. The first sub-gate electrode is located between the active layer, the source electrode, and the drain electrode in a film thickness direction of the TFT device. The second sub-gate electrode, the source electrode, and the drain electrode are disposed on a same layer. The second sub-gate electrode comprises two gate electrode metal patterns. The two gate electrode metal patterns are spaced apart and electrically connected to a same scan line and simultaneously charge the first sub-gate electrode.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first stack structure positioned on a first substrate, a first impurity region and a second impurity region respectively positioned on opposing sides of the first stack structure and operatively associated with the first stack structure, a second stack structure positioned above the first stack structure with a middle insulation layer interposed therebetween, and a third impurity region positioned on one side of the second stack structure and electrically coupled to the second impurity region. The first stack structure includes a plurality of first semiconductor layers and a plurality of gate assemblies alternatively arranged. The plurality of gate assemblies includes a gate dielectric and a gate electrode. The second stack structure includes a plurality of second semiconductor layers and a plurality of capacitor sub-units alternatively arranged.

Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form bottom gate electrodes having a first gate structure (40A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (46A-B) in the top Si/SiGe superlattice structures.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A memory circuit includes first and second active structures extending along a first direction. The first active structure has a shared source portion and first and second drain portions corresponding to source and drain nodes of first and second memory cells. The second active structure has a shared source portion and third and fourth drain portions corresponding to source and drain nodes of third and fourth memory cells. A first conductive structure extends along a second direction and electrically connects the shared source portions of the first and second active structures, and first and second bit lines extend over the first and second active structures. A via plug is part of a direct electrical connection between the first bit line and one of the first or second drain portions or between the second bit line and one of the third or fourth drain portions.

Abstract: An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design.

Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.

Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.

Abstract: A semiconductor device include a substrate including a peripheral region, a first active pattern provided on the peripheral region of the substrate, the first active pattern having an upper portion including first semiconductor patterns and second semiconductor patterns which are alternately stacked, a first gate electrode intersecting the first active pattern, a pair of first source/drain patterns provided at both sides of the first gate electrode, respectively, and a first gate insulating layer disposed between the first gate electrode and the first active pattern. The first gate insulating layer includes a first insulating layer formed on the first active pattern, a second insulating layer formed on the first insulating layer, and a high-k dielectric layer formed on the second insulating layer. The first gate insulating layer contains a first dipole element including lanthanum (La), aluminum (Al), or a combination thereof.

Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

Abstract: A method forms heterogeneous complementary FETs and a related semiconductor structure. The method comprises forming a layered nanosheet stack comprising two layers of a first channel material alternating with two layers of a second channel material, depositing a dielectric layer on a top layer of the nanosheet stack, and forming a checkered mask material with at least a first and a second row above the dielectric material. The first and the second row are distanced from each other. The method removes the first channel material and the second channel material outside an area of the checkered mask material, resulting in the at least a first row of pillars and a second row of pillars of layered nanosheet stacks. The method selectively removes in each of the pillars of the first stripe the second channel material.