Patents Examined by Tony Tran
  • Patent number: 11329217
    Abstract: A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: May 10, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Jorge Vasquez, Bartlomiej Adam Kardasz, Jacob Anthony Hernandez, Thomas D. Boone, Georg Wolf, Mustafa Pinarbasi
  • Patent number: 11319630
    Abstract: [Object] To make it difficult for components other than films to be contained in a lamination interface. [Solving Means] In a deposition apparatus, a vacuum chamber includes a partition wall which defines a plasma formation space and includes quartz. An deposition preventive plate is provided between at least a part of the partition wall and the plasma formation space and includes at least one of yttria, silicon nitride, or silicon carbide. On a support stage, a substrate including a trench or hole including a bottom portion and a side wall is capable of being disposed. A plasma generation source generates first plasma of deposition gas including silicon introduced into the plasma formation space to thereby form a semiconductor film including silicon on the bottom portion and the side wall. The plasma generation source generates second plasma of etching gas including halogen introduced into the plasma formation space to thereby selectively remove the semiconductor film formed on the side wall.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: May 3, 2022
    Assignee: ULVAC, INC.
    Inventor: Kazuhiko Tonari
  • Patent number: 11322535
    Abstract: A solid-state imaging device which includes a plurality of pixels in an arrangement, each of the pixels including a photoelectric conversion element, pixel transistors including a transfer transistor, and a floating diffusion region, in which the channel width of transfer gate of the transfer transistor is formed to be larger on a side of the floating diffusion region than on a side of the photoelectric conversion element.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: May 3, 2022
    Assignee: SONY CORPORATION
    Inventor: Yoshiharu Kudoh
  • Patent number: 11315826
    Abstract: A three-dimensional memory device includes a substrate, a plurality of horizontal conductive layers, a plurality of vertical memory structures and a vertical conductive post. The conductive layers are located above the substrate, and immediately-adjacent two of the conductive layers are spaced by a first air gap. The memory structures pass through the conductive layers and are connected to the substrate. The conductive post is located between immediately-adjacent two of the memory structures and passes through the conductive layers and is connected to the substrate. The conductive post is spaced from immediately-adjacent edges of the conductive layers by a second air gap.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: April 26, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 11302535
    Abstract: A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Po-Kang Ho
  • Patent number: 11282783
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure vertically extending through the alternating stack, and an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers. The perforated dielectric moat structure includes a plurality of lateral openings at each level of the insulating layers, and does not include any opening at levels of the electrically conductive layers.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: March 22, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoshitaka Otsu, Masanori Terahara, Junpei Kanazawa
  • Patent number: 11271163
    Abstract: In a method, a charged metal dot is deposited on a first position of a surface of a semiconductor substrate. Then, a charged region is formed on a second position of the surface of the semiconductor substrate, thereby establishing of which an electric field direction from the first position toward the second position. The first position is spaced apart from the second position by a distance. Thereafter, a precursor gas flows along the electric field direction on the semiconductor substrate, thereby forming a carbon nanotube (CNT) on the semiconductor substrate.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Martin Christopher Holland, Timothy Vasen, Blandine Duriez
  • Patent number: 11268334
    Abstract: Methods and systems for enhancing workflow performance in the oil and gas industry may estimate the properties of drilling muds (e.g., density and/or viscosity) located downhole with methods that utilize real-time data, estimated drilling mud properties, and mathematical models. Further, the methods described herein may optionally account for the uncertainties induced by sensor readings and dynamic modeling.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: March 8, 2022
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Xingyong Song, Jason D. Dykstra
  • Patent number: 11264518
    Abstract: A solar cell is fabricated by etching one or more of its layers without substantially etching another layer of the solar cell. In one embodiment, a copper layer in the solar cell is etched without substantially etching a topmost metallic layer comprising tin. For example, an etchant comprising sulfuric acid and hydrogen peroxide may be employed to etch the copper layer selective to the tin layer. A particular example of the aforementioned etchant is a Co-Bra Etch® etchant modified to comprise about 1% by volume of sulfuric acid, about 4% by volume of phosphoric acid, and about 2% by volume of stabilized hydrogen peroxide. In one embodiment, an aluminum layer in the solar cell is etched without substantially etching the tin layer. For example, an etchant comprising potassium hydroxide may be employed to etch the aluminum layer without substantially etching the tin layer.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: March 1, 2022
    Assignee: SunPower Corporation
    Inventors: Douglas H. Rose, Pongsthorn Uralwong, David D. Smith
  • Patent number: 11239098
    Abstract: According to one aspect of technique described herein, there is provided a technique including; a process chamber in which at least one substrate is processed; an electromagnetic wave supply part configured to supply an electromagnetic wave to the at least one substrate; a substrate holding part configured to hold the at least one substrate and at least one susceptor for suppressing the electromagnetic wave from being adsorbed to an edge of the at least one substrate; a substrate transfer part configured to transfer the at least one substrate; and a controller configured to control the substrate transfer part so as to correct a position of the at least one susceptor.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: February 1, 2022
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventor: Yukitomo Hirochi
  • Patent number: 11233091
    Abstract: A method for fabricating a semiconductor device including a resistive memory cell having a single fin includes concurrently forming a vertical transistor and a resistive element on a base substrate, including forming a first gate structure corresponding to a gate of the vertical transistor and a second gate structure corresponding to an electrode of the resistive element, forming a top source/drain layer on a fin formed on a bottom source/drain layer disposed on the base substrate, and forming a plurality of contacts. Forming the plurality of contacts includes forming a first contact corresponding to the first gate structure, a second contact corresponding to the top source/drain region and a third contact corresponding to the second gate structure.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: January 25, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kangguo Cheng
  • Patent number: 11211401
    Abstract: A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: December 28, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yao-An Chung, Yuan-Chieh Chiu, Ting-Feng Liao, Kuang-Wen Liu, Kuang-Chao Chen
  • Patent number: 11189606
    Abstract: A light emitting diode (LED) panel is provided. The LED panel includes a thin-film transistor (TFT) backplane which includes a plurality of LED bonding areas, and a plurality of LEDs which are respectively bonded to the plurality of LED bonding areas, wherein the plurality of LED bonding areas are formed to have different heights on the TFT backplane according to an LED type bonded thereto, and wherein a relatively thin LED from among the plurality of LEDs is bonded to an LED bonding area of a relatively low height from among the plurality of LED bonding areas.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: November 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangmin Shin, Hoseop Lee, Sangyoung Park
  • Patent number: 11168188
    Abstract: The process to fabricate a polymer film includes baking a cyclic olefin copolymer (COC) and a silicon wafer at a predefined temperature. The process also includes attaching a plastic tape frame to the silicon wafer and submerging the COC and the plastic tape frame within water allowing one or more ultra-thin sheets of COC film to be peeled off.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: November 9, 2021
    Assignee: United States of America as represented by the Administrator of NASA
    Inventors: Kevin L. Denis, Edward J. Wollack
  • Patent number: 11164796
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a work function material around a first semiconductor layer in a first region and a second semiconductor layer in a second region. The method also includes forming a first gate electrode material over the work function material. The method also includes removing the first gate electrode material in the first region. The method also includes forming a second gate electrode material over the work function material in the first region.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Patent number: 11158544
    Abstract: A method for forming a semiconductor device includes forming a structure having at least a first nanosheet stack for a first device, a second nanosheet stack for a second device and disposed over the first nanosheet stack, a disposable gate structure, and a gate spacer. The disposable gate structure and sacrificial layers of the first and second nanosheet stacks are removed thereby forming a plurality of cavities. A conformal gate dielectric layer is formed in the plurality cavities and surrounding at least portions of the first and second nanosheet stacks. A first conformal work function layer is formed in contact with the gate dielectric layer. Portions of the first conformal work function layer are removed without using a mask from at least the second nanosheet stack. A second conformal work function layer is formed on exposed portions of the gate dielectric layer.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Ruilong Xie, Chanro Park
  • Patent number: 11158541
    Abstract: A method of processing a wafer with a metal film to divide the wafer into individual device chips along a grid of projected dicing lines where the mechanical strength of the wafer is reduced. The method includes the steps of sticking a holding tape to a face side of the wafer, holding the wafer while a reverse side of the wafer with the metal film thereon is being exposed, and drawing the wafer under suction along the projected dicing lines to fracture the wafer along the projected dicing lines while the reverse side of the wafer is being cooled in its entirety.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 26, 2021
    Assignee: DISCO CORPORATION
    Inventor: Jinyan Zhao
  • Patent number: 11152407
    Abstract: An image sensor includes a first column line and a second column line configured to extend in a first direction, a plurality of pixel groups configured to connect to the first column line or the second column line and to comprise a plurality of pixels in each of the plurality of pixel groups, a bias circuit configured to comprise a first current circuit and a second current circuit configured to output different bias currents in a first operational mode, and a switching circuit configured to connect the first column line to the first current circuit and connect the second column line to the second current circuit during a first time period, and to connect the first column line to the second current circuit and connect the second column line to the first current circuit during a second time period subsequent to the first time period in the first operational mode.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: October 19, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Hong Kim, Dae Hwa Paik, Seung Hyun Lim, Sin Hwan Lim
  • Patent number: 11139369
    Abstract: A method of forming a semiconductor device includes forming a trench in a semiconductor body; at least partially filling the trench with a filling material, the filling material; introducing dopants into a portion of the filling material, where the dopants have a first diffusion coefficient relative to the filling material and have a second diffusion coefficient relative to the semiconductor body, where the first diffusion coefficient is greater than the second diffusion coefficient, and where a ratio of the first diffusion coefficient to the second diffusion coefficient is greater than 10; and applying thermal processing to the semiconductor body configured to spread the dopants in the filling material along a vertical direction between a bottom side and a top side of the filling material by a diffusion process.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 5, 2021
    Inventors: Reinhard Ploss, Hans-Joachim Schulze
  • Patent number: 11133028
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, the tunnel barrier layer is expressed by a chemical formula of AB2Ox, and has a spinel structure in which cations are arranged in a disordered manner, A represents a divalent cation that is either Mg or Zn, and B represents a trivalent cation that includes a plurality of elements selected from the group consisting of Al, Ga, and In.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 28, 2021
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki