Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a via, a liner layer, a barrier layer, and a conductor. The via penetrates through the substrate. The liner layer is formed on a sidewall of the via. The barrier layer is formed on the liner layer. The barrier layer comprises a conductive 2D material. The conductor fills a remaining space of the via.

Abstract: Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure.

Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.

Abstract: A three-dimensional (3D) semiconductor memory device includes electrode structures including a plurality of electrodes stacked on a semiconductor substrate, and the electrode structures extend in a first direction and are spaced apart from each other by separation regions in a second direction perpendicular to the first direction. The 3D semiconductor memory device includes ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures, wherein on a level of the ground select gate electrodes, the separation regions include a first end portion, and at least one ground select gate cutting region overlaps the first end portion of the separation regions and electrically isolates the ground select gate electrodes from each other.

Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, where the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.

Abstract: Some embodiments include a method in which a first stack is formed to include a metal-containing first layer, a second layer over the first layer, and a metal-containing third layer over the second layer. A first opening is formed to extend through the second and third layers. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. A second opening is formed through the second stack, and is extended through the sacrificial material. First semiconductor material is formed within the second opening. A third opening is formed through the second stack and to the second layer. The second layer is removed to form a conduit. Conductively-doped second semiconductor material is formed within the conduit. Dopant is out-diffused from the conductively-doped second semiconductor material into the first semiconductor material. Some embodiments include integrated assemblies.

Abstract: A method of forming a semiconductor device includes forming a trench in a semiconductor body; at least partially filling the trench with a filling material; introducing dopants into a portion of the filling material; and applying a first thermal processing to the semiconductor body to spread the dopants in the filling material along a vertical direction of the filling material by a diffusion process. The vertical doping profile of the dopants within the doped filling material is shaped during the first thermal processing. Additionally, the dopants are substantially confined to within the trench and substantially do not diffuse from the doped filling material into the semiconductor body during the first thermal processing. A second thermal processing is applied to the semiconductor body after the first thermal processing to cause diffusion of the dopants from the doped filling material into the semiconductor body adjoining the trench.

Abstract: According to one embodiment, a semiconductor memory device includes a first insulating layer; a first conductive layer provided in the first insulating layer and extending in the first direction; a second conductive layer extending in the first direction and provided adjacent to the first conductive layer in a second direction; and a contact plug coupled to one surface of the first conductive layer in a third direction. Thicknesses in the third direction of portions of the first and second conductive layers that overlap the contact plug in the third direction are smaller than thicknesses in the third direction of portions of the first and second conductive layers that do not overlap the contact plug in the third direction.

Abstract: The present disclosure provides a method for preparing a vertical memory structure with air gaps. The method includes providing a substrate; forming an impurity layer at an upper portion of the substrate; forming a semiconductor stack including a lower semiconductor pattern structure filling a recess on the substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate; forming a plurality of gate electrodes surrounding a sidewall of the semiconductor stack, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction; and forming a plurality of air gap structures disposed at outer sides of the plurality of gate electrodes respectively.

Abstract: An integrated transformer is provided. The integrated transformer includes a first inductor and second inductors. The first inductor includes a first winding having a first outer turn and a second winding having a second outer turn. The second inductor includes a third winding having a third outer turn and a fourth winding having a fourth outer turn. The first and third outer turns substantially overlap, and the second and fourth outer turns substantially overlap. The first and second outer turns are connected to each other through a first segment and a second segment that together form a crossing structure, and the third and fourth outer turns are connected to each other through a third segment and a fourth segment that together form a crossing structure. The first and third segments are in the first metal layer, while the second and fourth segments are in the second metal layer.

Abstract: A semiconductor storage device includes a substrate, a first stacked body provided above the substrate and having a side portion configured in a staircase pattern, a plurality of columnar portions passing through the first stacked body, a second stacked body provided in an outer edge portion of the substrate, and a plurality of first slits. The first stacked body include a plurality of first insulating layers and a plurality of conductive layers that are alternately stacked. The second stacked body includes the plurality of first insulating layers and the plurality of conductive layers that are alternately stacked. The plurality of first slits extends through the first and second stacked bodies in a direction intersecting a stacking direction of the first stacked body.

Abstract: A microelectronic device comprises pillar structures comprising semiconductive material, contact structures in physical contact with upper portions of the pillar structures, and conductive structures over and in physical contact with the contact structures. Each of the conductive structures comprises a lower portion having a first horizontal width, an upper portion vertically overlying the lower portion and having a second horizontal width greater than the first horizontal width, and an additional portion vertically interposed between the lower portion and the upper portion and having arcuate horizontal boundaries defining additional horizontal widths varying from the first horizontal width proximate the lower portion to a relatively larger horizontal width proximate the upper portion. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

Abstract: A nonvolatile memory device and method of fabricating same, the nonvolatile memory device including a substrate; a first semiconductor layer on the substrate; an etching stop film including a metal oxide on the first semiconductor layer; a mold structure including second semiconductor layers and insulating layers alternately stacked on the etching stop film; a channel hole penetrating through at least one of the mold structure, the etching stop film, the second semiconductor layer and the substrate; and a channel structure extending along a side wall of the channel hole, including an anti-oxidant film, a first blocking insulation film, a second blocking insulation film, a charge storage film, a tunnel insulating film and a channel semiconductor sequentially formed along the side wall of the channel hole. The first semiconductor layer contacts the first blocking insulation film, the second blocking insulation film, the charge storage film, and the tunnel insulating film.

Abstract: An electronic device comprises a stack structure comprising vertically alternating insulative structures and conductive structures arranged in tiers, pillars extending vertically through the stack structure, and a barrier material overlying the stack structure. The electronic device comprises a first insulative material extending through the barrier material and into an upper tier portion of the stack structure, and a second insulative material laterally adjacent to the first insulative material and laterally adjacent to at least some of the conductive structures in the upper tier portion of the stack structure. At least a portion of the second insulative material is in vertical alignment with the barrier material. Additional electronic devices and related methods and systems are also disclosed.

Abstract: Apparatuses, systems and methods associated with package substrate design with variable height conductive elements within a single layer are disclosed herein. In embodiments, a substrate may include a first layer, wherein a trench is located in the first layer, and a second layer located on a surface of the first layer. The substrate may further include a first conductive element located in a first portion of the second layer adjacent to the trench, wherein the first conductive element extends to fill the trench, and a second conductive element located in a second portion of the second layer, wherein the second conductive element is located on the surface of the first layer. Other embodiments may be described and/or claimed.

Abstract: Proposed is a method of preparing an independent free-standing graphene film. The graphene film is obtained by means of suction filtration of graphene oxide into a film, solid phase transfer, chemical reduction and the like steps. The graphene film is formed by means of physical cross-linking of a single layer of oxidized/reduced graphene oxide. The graphene film has a thickness of 10-2000 atomic layers. The graphene oxide film has a small thickness and a large number of defects inside, so that it has good transparency and excellent flexibility. On the basis of the transfer film-forming method above, an independent free-standing wrinkled graphene film having a nanoscale thickness is prepared by using a poor solvent and a special high temperature annealing process, and an independent free-standing foamed graphene film having a nanoscale thickness is obtained by using a film-forming thickness and a special high temperature annealing process.

Abstract: A semiconductor device structure includes a first chip, second chip, a first metal structure, a second metal structure, a first via structure and a second via structure. The first chip includes n inter metal dielectric (IMD) layer, which includes different materials adjacent to generate a number of staggered portions having a zigzag configuration. The second chip bonded to the first chip generates a bonding interface. The first metal structure is disposed in the first chip and between the staggered portions and the bonding interface. The first via structure in the first chip stops at the first metal structure. The first via structure includes a first via metal and a first via dielectric layer. A surface roughness of the staggered portions is substantially greater than a surface roughness of the first via dielectric layer. The second via structure extends from the first via structure to the second metal structure.

Abstract: A microelectronic device comprises a first deck structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, a second deck structure vertically overlying the first deck structure and comprising additional tiers of the conductive structures and insulative structures, a staircase structure within the first deck structure and having steps comprising edges of the tiers, a dielectric material covering the steps of the staircase structure and extending through the first deck structure, and a liner material interposed between the steps of the staircase structure and terminating at an interdeck region between the first deck structure and the second deck structure. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: Method for forming tungsten gap fill on a structure, including high aspect ratio structures includes depositing a tungsten liner in the structure using a physical vapor deposition (PVD) process with high ionization and an ambient gas of argon or krypton. The PVD process is performed at a temperature of approximately 20 degrees Celsius to approximately 300 degrees Celsius. The method further includes treating the structure with a nitridation process and depositing bulk fill tungsten into the structure using a chemical vapor deposition (CVD) process to form a seam suppressed boron free tungsten fill. The CVD process is performed at a temperature of approximately 300 degrees Celsius to approximately 500 degrees Celsius and at a pressure of approximately 5 Torr to approximately 300 Torr.