Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

Abstract: An image sensor includes a pixel array including a plurality of pixels arranged in a first direction and a second direction. Each pixel of the plurality of pixels includes a plurality of photodiodes disposed adjacent to one another in at least one of the first direction and the second direction. The image sensor further includes a control logic configured to generate image data by obtaining pixel signals from the plurality of pixels, and read a pixel voltage corresponding to charges generated by two or more of the plurality of photodiodes included in one of the plurality of pixels, at substantially the same time.

Abstract: A method of manufacturing a semiconductor device includes forming a first stack, forming a sacrificial structure and a first contact passing through the first stack, forming a second stack on the first stack, forming a first hole through the second stack to expose the sacrificial structure, forming a second hole through the first stack by removing the sacrificial structure, forming a channel structure in the first and second holes, and forming a second contact passing through the second stack and coupled to the first contact.

Abstract: Variable resistance devices and neural network processing systems include a first phase change memory device that has a first material that increases resistance when a set pulse is applied. A second phase change memory device has a second material that decreases resistance when a set pulse is applied.

Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, the tunnel barrier layer is expressed by a chemical formula of AB2Ox, and has a spinel structure in which cations are arranged in a disordered manner, A represents a divalent cation that is either Mg or Zn, and B represents a trivalent cation that includes a plurality of elements selected from the group consisting of Al, Ga, and In.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a finned dielectric moat structure including a dielectric core portion vertically extending through each layer within the alternating stack and a vertical stack of dielectric fin portions laterally extending outward from the dielectric core portion, a vertical stack of insulating plates and dielectric material plates laterally surrounded by the finned dielectric moat structure, and an interconnection via structure vertically extending through the vertical stack and contacting a top surface of an underlying metal interconnect structure.

Abstract: A semiconductor device includes a substrate material with a semiconductor material with a predetermined crystal orientation, a gate stack having a plurality of nanosheet channel layers, each nanosheet channel layer being controlled by metal gate layers located above and below the nanosheet channel layer, each nanosheet channel layer having the same semiconductor material and crystal orientation as that of the substrate, and a source/drain region on opposite sides of the gate stack. Each source/drain region includes bridging structures respectively connected to each nanosheet channel layer.

Abstract: Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects.

Abstract: An integrated circuit transformer (150) is formed with a primary winding (91) located in at least a first winding layer having a first thickness, a secondary winding (92) located in at least the first winding layer and having a first center point at the first side of the transformer and two secondary terminals at a second, opposite side of the transformer, and a first center tap feed line (81) located along a symmetry axis of the transformer in an upper metal layer having a second thickness that is at least equivalent to the first thickness of the first winding layer, wherein the first center tap feed line has a direct electrical connection to the first center point in the secondary winding.

Abstract: A semiconductor structure and its fabrication method are provided. The method includes: providing a substrate and a first metal layer in the substrate; forming a dielectric layer with a first opening exposing a portion of a top surface of the first metal layer on the substrate; bombarding the portion of the top surface of the first metal layer exposed by the first opening, by using a first sputtering treatment, to make metal materials on the top surface of the first metal layer be sputtered onto sidewalls of the first opening to form a first adhesion layer; and forming a second metal layer on a surface of the first adhesion layer and on the exposed portion of the top surface of the first metal layer using a first metal selective growth process.

Abstract: An ultra-large height top electrode for MRAM is achieved by employing a novel thin metal/thick dielectric/thick metal hybrid hard mask stack. Etching parameters are chosen to etch the dielectric quickly but to have an extremely low etch rate on the metals above and underneath. Because of the protection of the large thickness of the dielectric layer, the ultra-large height metal hard mask is etched with high integrity, eventually making a large height top electrode possible.

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and conductive rails laterally adjacent to the conductive structures of the stack structure. The conductive rails comprise a material composition that is different than a material composition of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

Abstract: A method of forming a microelectronic device comprises forming line structures comprising conductive material and insulative material overlying the conductive material, the line structures separated from one another by trenches. An isolation material is formed on surfaces of the line structures inside and outside of the trenches, the isolation material only partially filling the trenches to form air gaps interposed between the line structures. Openings are formed to extend through the isolation material and expose portions of the insulative material of the line structures. The exposed portions of the insulative material of the line structures are removed to form extended openings extending to the conductive material of the line structures. Conductive contact structures are formed within the extended openings. Conductive pad structures are formed on the conductive contact structures. Additional methods, microelectronic devices, memory devices, and electronic systems are also described.

Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.

Abstract: According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first metal portion, a third semiconductor region of a second conductivity type, a first electrode, a fourth semiconductor region of the second conductivity type, and a second electrode. The first semiconductor region includes a first portion and a second portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on part of the second semiconductor region. The first metal portion is provided in the first semiconductor region. The third semiconductor region is positioned on the first portion. The fourth semiconductor region is provided on another part of the second semiconductor region. The fourth semiconductor region is separated from the third semiconductor region. The fourth semiconductor region is positioned on the second portion.

Abstract: A method of manufacturing a light emitting device includes: placing a light-emitting element above a light-transmitting portion of a first resin layer; placing a protective element above the first resin layer or a first surface of the light-emitting element; forming a second resin layer on the first resin layer so as to cover an entirety of the light-emitting element and an entirety of the protective element; removing a portion of the second resin layer such that an anode and a cathode of the light-emitting element and a first electrically-conductive structure and a second electrically-conductive structure of the protective element are exposed from the second resin layer; and forming a first electrode, which is electrically connected to the anode and the first electrically-conductive structure, and a second electrode, which is electrically connected to the cathode and the second electrically-conductive structure.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a field effect transistor (FET) device on a substrate. The fabrication operations include forming a channel region over the substrate, forming a bottom conductive layer of a wrap-around source or drain (S/D) contact over the substrate, and forming a S/D region over the bottom conductive layer and adjacent to the channel region. The S/D region is communicatively coupled to the channel region and the bottom conductive layer.

Abstract: Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions.

Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.

Abstract: A method for producing optoelectronic semiconductor components may include applying optoelectronic semiconductor chips for generating radiation to a carrier, producing a potting around the semiconductor chips with a potting top side facing away from the carrier such that the semiconductor chips remain free of a reflective potting material. The potting has trenches between the semiconductor chips, and the trenches are arranged at a distance from the semiconductor chips; the trenches do not touch the semiconductor chips. The method may further include filling the trenches with a supporting material to form at least one supporting body and leaving the potting alongside the trenches free of the supporting material.