Abstract: A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.

Abstract: An apparatus includes a heterostructure including a substrate of Group-III-nitride material, a source layer including a dopant positioned on a surface of the substrate, and a conductive cap layer positioned on the source layer. A method of electric field-enhanced impurity diffusion includes obtaining a heterostructure including a substrate of Group-III-nitride semiconductor material, a source layer including a dopant positioned directly on the substrate, and a conductive cap layer positioned above the source layer, and applying a thermal annealing treatment to the heterostructure. An electric field gradient is established within the source layer and the cap layer for causing diffusion of an element from the substrate to the cap layer, and for causing diffusion of the dopant from the source layer to a former location of the element in the substrate thereby changing a conductivity and/or magnetic characteristic of the substrate.

Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer.

Abstract: A method for manufacturing a semiconductor device includes: forming a trimming element inside or over a semiconductor substrate; forming an insulating film on the trimming element; forming, on the insulating film, a first wiring layer connected to one end of the trimming element via a first contact region penetrating the insulating film; forming, on the insulating film, a second wiring layer connected to another end of the trimming element via a second contact region penetrating the insulating film; trimming the trimming element; and examining an insulated state between the semiconductor substrate and either the first wiring layer or the second wiring layer after the trimming.

Abstract: A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

Abstract: A TFT layer of a display device includes: an initialization power source wiring line; a second interlayer insulating film provided covering the initialization power source wiring line; a source wiring line provided on the second interlayer insulating film; a low-level power source wiring line provided below the initialization power source wiring line; and a frame capacitor. The frame capacitor includes: a first frame capacitance electrode formed by the same material in the same layer as the initialization power source wiring line; and a second frame capacitance electrode formed by the same material in the same layer as the source wiring line and facing the first frame capacitance electrode with the second interlayer insulating film interposed therebetween. The first frame capacitance electrode is electrically connected to the high-level power source wiring line, and the second frame capacitance electrode is electrically connected to the low-level power source wiring line.

Abstract: Method for forming tungsten gap fill on a structure, including high aspect ratio structures includes depositing a tungsten liner in the structure using a physical vapor deposition (PVD) process with high ionization and an ambient gas of argon or krypton. The PVD process is performed at a temperature of approximately 20 degrees Celsius to approximately 300 degrees Celsius. The method further includes treating the structure with a nitridation process and depositing bulk fill tungsten into the structure using a chemical vapor deposition (CVD) process to form a seam suppressed boron free tungsten fill. The CVD process is performed at a temperature of approximately 300 degrees Celsius to approximately 500 degrees Celsius and at a pressure of approximately 5 Torr to approximately 300 Torr.

Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

Abstract: In some implementations, one or more semiconductor processing tools may deposit cobalt material within a cavity of the semiconductor device. The one or more semiconductor processing tools may polish an upper surface of the cobalt material. The one or more semiconductor processing tools may perform a hydrogen soak on the semiconductor device. The one or more semiconductor processing tools may deposit tungsten material onto the upper surface of the cobalt material.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure including a dielectric fill material and vertically extending through the alternating stack. The perforated dielectric moat structure includes, at each level of the insulating layers, two rows of lengthwise dielectric pillar portions laterally extending along a first horizontal direction and two columns of widthwise dielectric pillar portions extending along a second horizontal directions that is perpendicular to the first horizontal direction. Each row of lengthwise dielectric pillar portions has a first center-to-center pitch. Each column of widthwise dielectric pillar portions has a second center-to-center pitch. A ratio of the second center-to-center pitch to the first center-to-center pitch is in a range from 1.50 to 2.0.

Abstract: A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.

Abstract: A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.

Abstract: An imaging device with reduced power consumption is provided. The imaging device includes an imaging portion and an encoder. First image data obtained by the imaging portion is transmitted to the encoder. The encoder includes a first circuit that forms a neural network, and the first circuit conducts feature extraction by the neural network on a first image to generate second image data. Note that since the first circuit has a function of performing convolution processing using a weight filter, the encoder can perform computation with a convolutional neural network.

Abstract: A semiconductor device may include a semiconductor substrate, a crack-blocking layer and a crack-blocking portion. The semiconductor substrate may include a plurality of chip regions and a scribe lane region configured to surround each of the plurality of the chip regions. A trench may be defined by one or more inner surfaces of the semiconductor device to be formed in the scribe lane region. The crack-blocking layer may be on an inner surface of the trench. The crack-blocking layer may be configured to block a spreading of a crack, which is generated in the scribe lane region during a cutting of the semiconductor substrate along the scribe lane region, from spreading into any of the chip regions. The crack-blocking portion may at least partially fill the trench and may be configured to block the spreading of the crack from the scribe lane region into any of the chip regions.

Abstract: A semiconductor device including an oxide semiconductor in which on-state current is high is provided. The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. Furthermore, the first transistor and the second transistor are transistors having a top-gate structure. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide semiconductor film which contain the impurity element function as low-resistance regions. Furthermore, the regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen. The first transistor provided in the driver circuit portion includes two gate electrodes between which the oxide semiconductor film is provided.

Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stacked body, an insulating layer overlapping the gate stacked body, a first source layer including a horizontal portion between the gate stacked body and the insulating layer and a protrusion extending from the horizontal portion so as to penetrate the insulating layer, a channel layer penetrating the gate stacked body and extending into the horizontal portion of the first source layer, a first memory pattern between the channel layer and the gate stacked body, and a second source layer disposed between the gate stacked body and the first source layer and coming in contact with the channel layer.

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, strings of memory cells vertically extending through the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, a conductive contact structure vertically overlying and in electrical communication with the channel material of a string of memory cells of the strings of memory cells, and a void laterally neighboring the conductive contact structure, the conductive contact structure separated from a laterally neighboring conductive contact structure by the void, a dielectric material, and an additional void laterally neighboring the laterally neighboring conductive contact structure. Related memory devices, electronic systems, and methods are also described.

Abstract: A light emitting diode (LED) panel is provided. The LED panel includes a thin-film transistor (TFT) backplane which includes an insulator film disposed on a top surface of a substrate, a plurality of organic films disposed on a top surface of the insulator film, and pixel electrodes disposed on a top surface of each of the plurality of organic films. The LED panel further includes a plurality of LEDs respectively bonded to the pixel electrodes disposed on the top surface of each of the plurality of organic films, wherein the plurality of organic films has the different heights according to a type of each of the plurality of LEDs respectively bonded to the pixel electrodes disposed on the top surface of each of the plurality of organic films.

Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

Abstract: A piezoelectric MEMS resonator is provided. The resonator comprises a single crystal silicon microstructure suspended over a buried cavity created in a silicon substrate and a piezoelectric resonance structure located on the microstructure. The resonator is designed and fabricated based on porous silicon related technologies including selective formation and etching of porous silicon in silicon substrate, porous silicon as scarified material for surface micromachining and porous silicon as substrate for single crystal silicon epitaxial growth. All these porous silicon related technologies are compatible with CMOS technologies and can be conducted in a standard CMOS technologies platform.