Abstract: An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.

Abstract: A semiconductor memory device includes a stacked body, a semiconductor member, and a first insulating member. Electrode films and insulating films are alternately stacked along a first direction in the stacked body. An end part of the stacked body is shaped like a staircase in which a terrace is formed for each of the electrode films. A portion of the electrode film placed in the end part is thicker than a portion of the electrode film placed in a central part of the stacked body. The semiconductor member extends in the first direction and penetrates through the central part of the stacked body. The first insulating member extends in the first direction and is provided in the end part.

Abstract: A method of fabricating a light emitting device package includes forming a plurality of semiconductor light emitting parts, each having a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on a growth substrate, forming a partition structure having a plurality of light emitting windows on the growth substrate, filling each of the plurality of light emitting windows with a resin having a phosphor, and forming a plurality of wavelength conversion parts by planarizing a surface of the resin.

Abstract: There is provided a vapor deposition mask including: a resin mask including a resin mask opening corresponding to a pattern to be produced by vapor deposition; and a metal layer partially positioned on one surface of the resin mask.

Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

Abstract: A ferroelectric memory device includes a substrate having a source region and a drain region, a ferroelectric structure having a first ferroelectric material layer, an electrical floating layer, and a second ferroelectric material layer sequentially stacked on the substrate, and a gate electrode layer disposed on the ferroelectric structure. A coercive electric field of the first ferroelectric material layer is different from that of the second ferroelectric material layer, and the electrical floating layer comprises a conductive material.

Abstract: A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.

Abstract: An RC-IGBT includes a first electrode disposed on a first main surface of a semiconductor substrate over a transistor region and a diode region. The semiconductor substrate includes a MOS gate structure on a first main surface side in the transistor region. The RC-IGBT includes: an interlayer dielectric covering a gate electrode of the MOS gate structure, and having a contact hole exposing a semiconductor layer; and a barrier metal disposed in the contact hole. The first electrode enters the contact hole, is in contact with the semiconductor layer of the MOS gate structure through the barrier metal, and is in direct contact with a semiconductor layer in the diode region of the semiconductor substrate.

Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, wherein the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.

Abstract: An integrated circuit containing finFETs may be formed with fins extending above isolation oxide. A first finFET and a second finFET have exposed fin heights which are different by at least 25 percent. The exposed fin height is a vertical height of a sidewall of the fin above the isolation oxide. Gates are formed over the fins. In one version, a fin height of the first finFET is less than a fin height of the second finFET; a thickness of the isolation oxide adjacent to fins of the first finFET and the second finFET is substantially uniform. The fin height is the height of a top of the fin above the substrate. In another version, the isolation oxide is thinner at the first finFET than at the second finFET; the fin heights of the first finFET and the second finFET are substantially equal.

Abstract: A radio frequency (RF) switch includes a heating element, an aluminum nitride layer situated over the heating element, and a phase-change material (PCM) situated over the aluminum nitride layer. An inside segment of the heating element underlies an active segment of the PCM, and an intermediate segment of the heating element is situated between a terminal segment of the heating element and the inside segment of the heating element. The aluminum nitride layer situated over the inside segment of the heating element provides thermal conductivity and electrical insulation between the heating element and the active segment of the PCM. The aluminum nitride layer extends into the intermediate segment of the heating element and provides chemical protection to the intermediate segment of the heating element, such that the intermediate segment of the heating element remains substantially unetched and with substantially same thickness as the inside segment.

Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

Abstract: A method of forming a semiconductor device that includes forming a stack of nanosheets composed of a semiconductor material; and forming a sacrificial layer of a work function adjusting material on the semiconductor material of the stack of nanosheets. In a following step, the work function adjusting material is mixed into the semiconductor material on at least a channel surface of nanosheets. The sacrificial layer is removed. An interfacial oxide layer is formed including elements from the semiconductor material and the work function adjusting layer on said at least the channel surface of the stack of nanosheets. A gate structure including a gate dielectric is formed on the interfacial oxide that is present on the channel surface of the nanosheets.

Abstract: In case the size of the transistor is enlarged, power consumption of the transistor is increased. Thus, the present invention provides a display device capable of preventing a current from flowing to a display element in signal writing operation without varying potentials of power source lines for supplying a current to the display element per row. In setting a gate-source voltage of a transistor by applying a predetermined current to the transistor, a potential of a gate terminal of the transistor is adjusted so as to prevent a current from flowing to a load connected to a source terminal of the transistor. Therefore, a potential of a wire connected to the gate terminal of the transistor is differentiated from a potential of a wire connected to a drain terminal of the transistor.

Abstract: To form p-type semiconductor regions in a gallium nitride (GaN)-based semiconductor by ion implantation. A method for manufacturing a semiconductor device comprises forming first grooves, depositing, and ion-implanting. At the step of forming the first grooves, the first grooves are formed in a stacked body including a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity. The first grooves each have a bottom portion located in the first semiconductor layer. At the depositing step, the p-type impurity is deposited on side portions and the bottom portions of the first grooves. At the ion-implanting step, the p-type impurity is ion-implanted into the first semiconductor layer through the first grooves.

Abstract: Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions.

Abstract: The invention relates to a flexible printed-circuit strip to whose upper face and/or lower face electronic components can be or are mounted, wherein it is subdivided in the direction of its longitudinal extension (L) into first and second surface zones (F1, F2) and it is subdivided perpendicular to the longitudinal direction (L) into a first edge region (SB1) and a second edge region (SB2), the two strip portions (SB1, SB2) being on both sides of a common longitudinal line (LL), wherein all the first surface zones (F1) are arranged in the first edge region (SB1) and all the second surface zones (F2) are arranged in the second edge region (SB2), and wherein first and second surface zones (F1, F2) that are adjacent in longitudinal direction (L) are respectively connected by a connecting web (V) that crosses the longitudinal line (LL).

Abstract: A method for forming self aligned magnetic memory element pillars for Magnetic Random Access Memory. The method allows the magnetic memory element pillars to be arranged in staggered rows of memory elements at a pitch that is smaller than what is possible using photolithography alone. The method involves forming a spacer mask in the form of an array of connected rings arranged in a square pattern of non-staggered rows. A sacrificial mask material is deposited over the spacer mask and the spacer mask is then removed, leaving sacrificial mask material in the holes at the center of the rings and also in the spaces between the rings. A reactive ion processes is then performed to transfer the pattern of the sacrificial mask onto underlying hard mask layers. A material removal process can then be performed to define a plurality of memory element pillars.

Abstract: Provided herein are tapered nanowires that comprise germanium and gallium, as well as methods of forming the same. The described nanowires may also include one or more sections of a second semiconductor material. Methods of the disclosure may include vapor-liquid-solid epitaxy with a gallium catalyst. The described methods may also include depositing a gallium seed on a surface of a substrate by charging an area of the substrate using an electron beam, and directing a gallium ion beam across the surface of the substrate.

Abstract: A stacked III-V semiconductor diode having an n? layer having a first surface, a second surface, a dopant concentration of 1012 N/cm3 to 1017 N/cm3 and a layer thickness of 50 ?m to 1,000 ?m, a p+ layer, which is integrally connected to the first surface and has a dopant concentration of 5·1018 N/cm3 to 5·1020 N/cm3, an n+ layer, which is integrally connected to the second surface and has a dopant concentration of at least 1019 N/cm3. The p+ layer, the n? layer and the n+ layer each having a monolithic design and each being made up of a GaAs compound. The dopant concentration of the n? layer having a first value on the first surface and a second value on the second surface, and the second value of the dopant concentration being greater than the first value at least by a factor between 1.5 and 2.5.