Patents Examined by Tracy A Warren
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Patent number: 10416905Abstract: An example method of controlling a storage system that includes a replication group. The method may include adding a virtual volume to the replication group by storing a journal entry for the virtual volume at a source site. The journal entry may include: metadata for hooking the virtual volume to a corresponding replica volume; and data indicating a status of the virtual volume. The method may further include sending a message to a replica site instructing it to create the corresponding replica volume for the virtual volume and store a replica journal entry for the replica volume. The method may also include determining whether to set the status of the virtual volume to pending admittance or newly admitted based on whether the replica site was able to successfully create the replica volume and store the replica journal entry.Type: GrantFiled: February 9, 2017Date of Patent: September 17, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Nathaniel Rogers, Sonali Somyalipi, Robert Neal-Joslin, Lisa Liu, Sujatha Mudupalli
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Patent number: 10409714Abstract: One potential result of differing characteristics for certain two-terminal memory (TTM) is that memory management techniques, such as logical-to-physical (L2P), can differ as well. Previous memory management techniques do not adequately leverage the advantages associated with TTM. For example, by identifying and leveraging certain advantageous characteristics of TTM, L2P tables can be designed to be smaller and more efficient, which can allow the L2P table to be stored in memory that is faster and/or closer (or integrated into) an associated controller. Moreover, other memory management operations such as wear-leveling, recovery from power loss, and so forth, can be more efficient.Type: GrantFiled: February 9, 2017Date of Patent: September 10, 2019Assignee: Crossbar, Inc.Inventors: Ruchirkumar Shah, Mehdi Asnaashari
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Patent number: 10402326Abstract: A system that includes circuitry to access memories in both coherent and non-coherent domains is disclosed. The circuitry may receive a command to access a memory included in the coherent domain and generate one or more commands to access a memory in the non-coherent domain dependent upon the received command. The circuitry may send the generated one or more commands to the memory in the non-coherent domain via communication bus.Type: GrantFiled: April 26, 2016Date of Patent: September 3, 2019Assignee: Apple Inc.Inventors: Ronald P. Hall, Mahesh K. Reddy, David J. Williamson
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Patent number: 10394486Abstract: The invention introduces a method for GC (Garbage Collection) in a flash memory, performed by a processing unit, including at least the following steps: reading n×m pages of good data from storage sub-units, wherein n indicates the quantity of storage sub-units sharing one channel and m indicates the quantity of pages for programming data into one storage sub-unit; and repeatedly performing a loop for directing each of the storage sub-units to program m pages of good data until all of the storage sub-units are operated in busy states.Type: GrantFiled: November 11, 2016Date of Patent: August 27, 2019Assignee: Silicon Motion, Inc.Inventor: Shen-Ting Chiu
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Patent number: 10387303Abstract: A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations.Type: GrantFiled: August 9, 2017Date of Patent: August 20, 2019Assignee: Western Digital Technologies, Inc.Inventors: Pankaj Mehra, Vidyabhushan Mohan, Seung-Hwan Song, Dejan Vucinic, Chao Sun, Minghai Qin, Arup De
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Patent number: 10380030Abstract: A data processing apparatus comprising: at least one initiator device for issuing transactions, a hierarchical memory system comprising a plurality of caches and a memory and memory access control circuitry. The initiator device identifies storage locations using virtual addresses and the memory system stores data using physical addresses, the memory access control circuitry is configured to control virtual address to physical address translations. The plurality of caches, comprise a first cache and a second cache. The first cache is configured to store a plurality of address translations of virtual to physical addresses that the initiator device has requested. The second cache is configured to store a plurality of address translations of virtual to physical addresses that it is predicted that the initiator device will subsequently request. The first and second cache are arranged in parallel with each other such that the first and second caches can be accessed during a same access cycle.Type: GrantFiled: December 5, 2012Date of Patent: August 13, 2019Assignee: ARM LimitedInventor: Nitin Isloorkar
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Patent number: 10372631Abstract: A computer-implemented method sanitizes memory in a cloud environment. One or more processors in a computer receive a hypercall resulting from a call from an application running in a computer. The hypercall is to a hypervisor that manages a virtual memory. The hypercall directs the hypervisor to sanitize data in the virtual memory, where sanitizing the data applies a data remanence policy that prevents remanence data in the virtual memory from being accessed by an unauthorized user. In response to receiving the hypercall, one or more processors sanitize the data in the virtual memory that is allocated for use by the application.Type: GrantFiled: February 9, 2017Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Suresh N. Chari, Ashish Kundu, Dimitrios Pendarakis
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Patent number: 10365836Abstract: An apparatus includes: an adaptive declustered RAID array configured of data storage devices (DSDs), the DSDs comprise data chunks allocated as data, a local parity, or a global parity; and a controller configured to generate a reliability indicator reflective of a reliability status of at least a portion of the adaptive declustered RAID array for reallocating the data chunks by dynamically increasing or decreasing the data chunks allocated as the local parity, the global parity, or a combination thereof.Type: GrantFiled: January 27, 2015Date of Patent: July 30, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Jun Xu, Wei Xi, Grant Mackey, Sanghoon Chu, Jie Yu
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Patent number: 10359972Abstract: A storage module may be configured to service I/O requests according to different persistence levels. The persistence level of an I/O request may relate to the storage resource(s) used to service the I/O request, the configuration of the storage resource(s), the storage mode of the resources, and so on. In some embodiments, a persistence level may relate to a cache mode of an I/O request. I/O requests pertaining to temporary or disposable data may be serviced using an ephemeral cache mode. An ephemeral cache mode may comprise storing I/O request data in cache storage without writing the data through (or back) to primary storage. Ephemeral cache data may be transferred between hosts in response to virtual machine migration.Type: GrantFiled: March 14, 2013Date of Patent: July 23, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Vikram Joshi, David Flynn, Yang Luan, Michael F. Brown
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Patent number: 10346309Abstract: In an embodiment, a prefetch circuit may implement prefetch “boosting” to reduce the cost of cold (compulsory) misses and thus potentially improve performance. When a demand miss occurs, the prefetch circuit may generate one or more prefetch requests. The prefetch circuit may monitor the progress of the demand miss (and optionally the previously-generated prefetch requests as well) through the cache hierarchy to memory. At various progress points, if the demand miss remains a miss, additional prefetch requests may be launched. For example, if the demand miss accesses a lower level cache and misses, additional prefetch requests may be launched because the latency avoided in prefetching the additional cache blocks is higher, which may over ride the potential that the additional cache blocks are incorrectly prefetched.Type: GrantFiled: April 26, 2017Date of Patent: July 9, 2019Assignee: Apple Inc.Inventors: James R. Hakewill, Ian D. Kountanis, Douglas C. Holman
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Patent number: 10346095Abstract: A storage module may be configured to service I/O requests according to different persistence levels. The persistence level of an I/O request may relate to the storage resource(s) used to service the I/O request, the configuration of the storage resource(s), the storage mode of the resources, and so on. In some embodiments, a persistence level may relate to a cache mode of an I/O request. I/O requests pertaining to temporary or disposable data may be serviced using an ephemeral cache mode. An ephemeral cache mode may comprise storing I/O request data in cache storage without writing the data through (or back) to primary storage. Ephemeral cache data may be transferred between hosts in response to virtual machine migration.Type: GrantFiled: March 14, 2013Date of Patent: July 9, 2019Assignee: SANDISK TECHNOLOGIES, LLCInventors: Vikram Joshi, David Flynn, Yang Luan, Michael F. Brown
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Patent number: 10331364Abstract: A system configuration containing a host, solid state drive (“SSD”), and controller able to perform a hybrid mode non-volatile memory (“NVM”) access is disclosed. Upon receiving a command with a logical block address (“LBA”) for accessing information stored in NVM, a secondary flash translation layer (“FTL”) index table is loaded to a first cache and entries in a third cache is searched to determine validity associated with stored FTL table. When the entries in the third cache are invalid, the FTL index table in the second cache is searched to identify valid FTL table entries. If the second cache contains invalid FTL index table, a new FTL index table is loaded from NVM to the second cache. The process subsequently loads at least a portion of FTL table indexed by the FTL index table in the third cache.Type: GrantFiled: October 14, 2016Date of Patent: June 25, 2019Assignee: CNEX Labs, Inc.Inventor: Yiren Ronnie Huang
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Patent number: 10289340Abstract: Systems, methods and/or devices are used to coalesce metadata and data writes via write serialization with device-level address remapping. In one aspect, a method of managing a storage system having one or more storage devices includes a serialized write operation to the storage system, in which a serialization segment accumulates data objects and mapping information until the segment is full, at which time the serialization segment is written to the storage system in a single contiguous write. As a result, the number of I/O operations is decreased from a minimum of two (one to write data and one to write updated mapping information) to a single write operation. Further, if the serialization segment contains existing valid data prior to accumulating data objects and mapping information, the valid data is moved to the beginning of the serialization segment using either a remap or xcopy operation.Type: GrantFiled: February 8, 2017Date of Patent: May 14, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Brian W. O'Krafka, Johann George, Vladislav Bolkhovitin, Manavalan Krishnan, Evgeniy Firsov
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Patent number: 10289303Abstract: A flash controller and a control method for the flash controller. The flash controller comprises an instruction bus interface, a data bus interface, a configuration register, an erase access filter module, a read/write access filter module and a flash control module. The read/write access filter module is configured to receive control information and determine whether the read/write access is sent to the flash control module or not. The erase access filter module is configured to receive control information and determine whether the erase access is sent to the flash control module or not. The flash control module is configured to complete an access to a flash memory. The present disclosure is used to protect programs from being stolen by a client, and also protect against a situation where companies collaboratively developing a program are able to steal programs from one another.Type: GrantFiled: January 30, 2015Date of Patent: May 14, 2019Assignee: GIGADEVICE SEMICONDUCTOR (BEIJING) INC.Inventors: Baokui Li, Jinghua Wang, Nanfei Wang
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Patent number: 10282292Abstract: Cluster manager functional blocks perform operations for migrating pages in portions in corresponding migration clusters. During operation, each cluster manager keeps an access record that includes information indicating accesses of pages in the portions in the corresponding migration cluster. Based on the access record and one or more migration policies, each cluster manager migrates pages between the portions in the corresponding migration cluster.Type: GrantFiled: October 17, 2016Date of Patent: May 7, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Andreas Prodromou, Mitesh R. Meswani, Arkaprava Basu, Nuwan S. Jayasena, Gabriel H. Loh
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Patent number: 10275359Abstract: The present disclosure provides a cache cleaning method, a cache cleaning apparatus and a client, which improves a cache cleaning efficiency in a client and improves a user experience effectively. The method includes: detecting an amount of used caches in a mobile terminal; if the amount of used caches is larger than a preset threshold, sending a cache application request to an operating system of the mobile terminal so as to trigger a preset cache release rule in the operating system; and after the operating system releases corresponding caches according to the preset cache release rule, sending a cache release request to the operating system such that the operating system releases caches allocated for the cache application request according to the cache release request. The present disclosure may be used in a cache management technique of a mobile terminal.Type: GrantFiled: August 13, 2014Date of Patent: April 30, 2019Assignee: SHELL INTERNET (BEIJING) SECURITY TECHNOLOGY CO., LTD.Inventors: Yi Dong, Hang Wei, Dingpan Li, Jian Ma
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Patent number: 10268373Abstract: According to one embodiment, there is provided a storage system comprising a storage unit including a memory unit, the memory unit including a nonvolatile memory, a controller and a first issuance unit, wherein the controller controls the nonvolatile memory. The system also comprises a connection unit which controls the storage unit. Further the system comprises a first power supply unit which supplies a first power supply voltage to the storage unit and/or to the connection unit, the first power supply voltage being generated by converting an external power supply voltage. Additionally, the system comprises a management unit which monitors power supply information based on the first power supply voltage. The connection unit issues a first write request for writing first data to the memory unit, and the first issuance unit issues, to the connection unit, first information associated with the first data of the write request.Type: GrantFiled: April 28, 2015Date of Patent: April 23, 2019Assignee: Toshiba Memory CorporationInventor: Shinichiro Manabe
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Patent number: 10261910Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.Type: GrantFiled: March 22, 2016Date of Patent: April 16, 2019Assignee: QUALCOMM IncorporatedInventors: Andrew Edmund Turner, George Patsilaras, Bohuslav Rychlik
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Patent number: 10248345Abstract: Disclosed herein are methods, systems, and processes to persist data as information. A logical container is created. The logical container is dynamically defined to correspond to a storage device. Original data or encoded data written by an application container is received. If original data is received, encoded data is generated from original data. If encoded data is received, original data is generated from encoded data. Generating encoded data from original data, and original data from encoded data involves calculating original metadata for original data, and encoded metadata for encoded data. Encoded data or original data along with original metadata and encoded metadata is transported through the logical container past a persistence boundary. In response to transporting past the persistence boundary, a confirmation is received original data has been persisted.Type: GrantFiled: February 26, 2016Date of Patent: April 2, 2019Assignee: Veritas Technologies LLCInventor: Christopher M. Dickson
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Patent number: 10241675Abstract: A method is provided for rebuilding a flash translation layer table of a solid state drive. The superblock includes plural superpages. Each of the plural superpages includes plural physical pages. The method includes steps of confirming if the flash translation layer table is lost or not after the solid state drive is powered on; if the flash translation layer table is lost, starting a superblock scanning method for determining a status of the superblock; and rebuilding the flash translation table according to the status of the superblock. The superblock scanning method includes steps of reading contents of a first physical page and a last physical page of a last superpage in the superblock, and determining a status of the superblock according to the contents of the first physical page and the last physical page.Type: GrantFiled: October 17, 2016Date of Patent: March 26, 2019Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATIONInventors: Yu-Chuang Peng, Min-I Hung