Patents Examined by Tracy C Chan
  • Patent number: 10620858
    Abstract: A data storage method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a first space in a first physical unit of a rewritable non-volatile memory module; and storing at least part of data stored in at least one physical unit of the rewritable non-volatile memory module to a second space in the first physical unit, and the second space is not belonging to the first space, and the first space is for ensuring that valid data stored in at least one second physical unit among the at least one physical unit can be stored to the first physical unit. Therefore, it is ensured that at least one spare physical unit of the memory storage device can be released by a data merging operation of multiple source nodes.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: April 14, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10621115
    Abstract: A system and method for communication link management in a credit-based system is disclosed. In one embodiment, a system includes first and second functional circuit blocks implemented on an integrated circuit and being able to communicate with one another through establishment of source synchronous links. The first functional circuit block includes a write queue for storing data and information regarding write requests sent from the second functional circuit block. The write queue includes credit management circuitry arranged to convey one or more credits to the second functional circuit block responsive to receiving one or more write requests therefrom. Responsive to receiving the one or more credits and in the absence of any pending additional requests, the second functional circuit block may deactivate a link with the first functional circuit block.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 14, 2020
    Assignee: Apple Inc
    Inventors: Gregory S. Mathews, Shane J. Keil, Lakshmi Narasimha Nukala
  • Patent number: 10599360
    Abstract: A system and method of data transmission are disclosed. In certain aspects, the method, performed by a target node, includes receiving a first plurality of hash values from the source node and comparing the first plurality of hash values with a second plurality of hash values. The method also includes determining a set of common hash values corresponding to an intersection of the first plurality of hash values and the second plurality of hash values. The method further includes reserving the set of common hash values by placing the set of common hash values in a first filter stored in a memory of the target node and committing the set of common hash values by placing them in a second filter stored in a storage of the target node.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 24, 2020
    Assignee: VMware, Inc.
    Inventors: Vijay Somasundaram, Sudarshan Madenur Sridhara
  • Patent number: 10579270
    Abstract: A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. Moreover, the program instructions are readable and/or executable by a processor to cause the processor to perform a method which includes: maintaining a first open logical erase block for user writes, and a second open logical erase block for relocate writes. A first data stream having the user writes is received, and transferred to the first open logical erase block. A second data stream having the relocate writes is also received, and transferred to the second open logical erase block. Furthermore, a third data stream is received, and is mixed with the first, second, and/or another data stream in response to determining that an open logical erase block is not available for assignment to the third data stream.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Roman A. Pletka, Sasa Tomic
  • Patent number: 10579541
    Abstract: A control device includes a cache memory configured to store a first, a second, a third and a fourth list, each of the first, the second, the third and the fourth list storing information indicating data stored in the cache memory, and each of the first, the second, the third and the fourth list being managed under a LRU algorithm, and when first data stored in the storage device is accessed, register first information indicating the first data into the first list, and when the first data is stored in the storage device, register second information indicating the first data into the second list, a processor coupled to the memory and configured to receive a first request for reading the first data, and based on the first request, move the first information from the first list to the third list, while remain the second information in the second list.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: March 3, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Jun Kato
  • Patent number: 10564886
    Abstract: Aspects of the disclosure provide for control of a flash translation layer (FTL) in a non-volatile memory (NVM). Disclosed methods and apparatus provide for receiving a message in the FTL, which is transmitted from a host device, and includes desired recycle ratio information that is determined by the host where the ratio is a number of host writes to a number of recycle writes to be performed by the FTL. Based on the recycle ratio information, the FTL determines a target recycle ratio and performs recycling of memory blocks in the NVM based on the determined target recycle ratio. In this manner, the host device is able to exert control over the recycle ratio utilized in the FTL via a transmitted message, which allows the recycle ratio to be more adaptive to host write conditions known to the host device, but not known in the SSD.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Saugata Das Purkayastha
  • Patent number: 10565129
    Abstract: In various examples a compute node is described. The compute node has a central processing unit which implements a hardware transactional memory using at least one cache of the central processing unit. The compute node has a memory in communication with the central processing unit, the memory storing information comprising at least one of: code and data. The compute node has a processor which loads at least part of the information, from the memory into the cache. The processor executes transactions using the hardware transactional memory and at least the loaded information, such that the processor ensures that the loaded information remains in the cache until completion of the execution.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: February 18, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Felix Schuster, Olga Ohrimenko, Istvan Haller, Manuel Silverio da Silva Costa, Daniel Gruss, Julian Lettner
  • Patent number: 10558398
    Abstract: Systems and methods for reducing read latency by storing a redundant copy of data are described. In one embodiment, the systems and methods include identifying data assigned to be written to a page of a storage device, storing the data in a page of a first die of the storage device, and saving at least one codeword from the data to a page of a second die. In some embodiments, the first die is associated with a first channel of the storage device and the second die is associated with a second channel of the storage device.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: February 11, 2020
    Assignee: Seagate Technology LLC
    Inventors: Kevin A. Gomez, Mark Ish, David S. Ebsen, Daniel J. Benjamin
  • Patent number: 10552316
    Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe D'Eliseo, Luigi Esposito, Xinghui Duan, Lucia Santojanni, Massimo Iaculo
  • Patent number: 10534713
    Abstract: Modifying prefetch request processing. A prefetch request is received by a local computer from a remote computer. The local computer responds to a determination that execution of the prefetch request is predicted to cause an address conflict during an execution of a transaction of the local processor by determining an evaluation of the prefetch request prior to execution of the program instructions included in the prefetch request. The evaluation is based, at least in part, on (i) a comparison of a priority of the prefetch request with a priority of the transaction and (ii) a condition that exists in one or both of the local processor and the remote processor. Based on the evaluation, the local computer modifies program instructions that govern execution of the program instructions included in the prefetch request.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
  • Patent number: 10534750
    Abstract: According to one set of embodiments, a computer system can receive a request/command to delete a snapshot from among a plurality of snapshots of a dataset that are stored in cloud/object storage. In response, the computer system can determine a first minimum chunk identifier (ID) and a first maximum chunk ID of a range of data chunks referred to by the first snapshot, and a second minimum chunk ID and a second maximum chunk ID of a range of data chunks referred to by an immediate child snapshot of the first snapshot. The computer system can then, for each data chunk identified by a chunk ID spanning from the second minimum chunk ID to the first maximum chunk ID, check whether the data chunk is referred to by the immediate child snapshot and if not, delete the data chunk from the cloud/object storage.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: January 14, 2020
    Assignee: VMware, Inc.
    Inventors: Pooja Sarda, Satish Kumar Kashi Visvanathan, Arun Kandambakkam
  • Patent number: 10514971
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device obtains directory metrics associated with a directory structure that is associated with a directory file that is segmented into a plurality of data segments and based on a determination to reconfigure the directory structure based on the directory metrics, the computing device determines a number of layers for a reconfigured directory structure, a number of spans per layer of the number of layers for the reconfigured directory structure, and directory entry reassignments. The computing device reconfigures the directory structure based on the number of layers, the spans per layer, and the directory entry reassignments.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: December 24, 2019
    Assignee: PURE STORAGE, INC.
    Inventors: Jason K. Resch, Wesley B. Leggette, Andrew D. Baptist, Ilya Volvovski, Greg R. Dhuse
  • Patent number: 10509564
    Abstract: A request to generate a storage system model is received. The storage system model represents at least a portion of a storage system. In response to receiving the request, a storage system interface configuration is loaded. The storage system interface configuration comprises an attribute of an entity model. The attribute corresponds to an attribute of a storage system entity of the storage system. Further in response to receiving the request, the entity model is identified as representing the storage system entity. In response to identifying the entity model as representing the storage system entity, the entity model is instantiated.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: December 17, 2019
    Assignee: NetApp Inc.
    Inventors: Brian Joseph McGiverin, Christopher Michael Morrissey, Daniel Andrew Sarisky, Santosh C. Lolayekar
  • Patent number: 10509578
    Abstract: A request to provide storage resources for an application may be received and storage resource pools that are available to provide storage resources may be identified. A determination may be made as to whether any of the storage resource pools has an available amount of storage resources to provide the requested amount of storage resources for the application. If none have the available amount of storage resources, then two or more of the storage resources may be identified in view of an amount of available storage resources available at each of the storage resource pools. A logical address space may be created in view of the two or more storage resource pools.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: December 17, 2019
    Assignee: Red Hat, Inc.
    Inventor: Huamin Chen
  • Patent number: 10474374
    Abstract: A storage device (220) is described. The storage device (220) may store data in a storage memory (445), and may have a host interface (420) to manage communications between the storage device (220) and a host machine (110, 115, 120, 125, 130). The storage device (220) may also include a translation layer (430) to translate addresses between the host machine (110, 115, 120, 125, 130) and the storage memory (445), and a storage interface (440) to access data from the storage memory (445). An in-storage monitoring engine (425) may determine characteristics (605, 610, 615) of the storage device (220), such as latency (605), bandwidth (610), and retention (615).
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Inseok Stephen Choi, Yang Seok Ki, Byoung Young Ahn
  • Patent number: 10459797
    Abstract: A dispersed storage network (DSN) includes receiving a slice access request including a slice name, identifying a sub-range of a DSN address range based on the slice name, identifying a memory device of a group of memory devices associated with the sub-range utilizing a decentralized agreement function based on the slice name, facilitating a slice access request with the identified memory device. For rebuilding a slice, a method includes detecting a storage error, identifying a sub-range of the DSN address range, facilitating rebuilding of the identified sub-range to produce rebuilt encoded data slices, updating location weights of the group of memory devices based on the detected storage error, for each rebuilt encoded data slice, identifying a corresponding memory device of the group of memory devices for storage of the rebuilt encoded data slice utilizing the decentralized agreement function and the updated location weights, and storing the rebuilt encoded data slice.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 29, 2019
    Assignee: PURE STORAGE, INC.
    Inventors: Jason K. Resch, Thomas D. Cocagne, Wesley B. Leggette
  • Patent number: 10452297
    Abstract: The method and system generates a first deduplication map (DDM) level including first data and a second DDM level including second data. The method or apparatus also generates a first index summary (IS) level corresponding to the first DDM level and a second IS level corresponding to the second DDM level. The method or apparatus merges the first data of the first DDM level and the second data of the second DDM level to generate a third DDM level comprising third data. The method or apparatus in response to generating the third DDM level, generates a third IS level to accelerate lookup within the third DDM level.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 22, 2019
    Assignee: Pure Storage, Inc.
    Inventors: Ronald Karr, Ethan L. Miller, Cary A. Sandvig, Feng Wang, Wei Zhang
  • Patent number: 10447612
    Abstract: A method begins by a processing module of a dispersed storage network (DSN) identifying a change in DSN memory of the DSN. For a set of encoded data slices effected by the change, the method continues with the processing module ascertaining updated properties of the DSN memory and performing an updating scoring function using properties of DSN access information and the updated properties of the DSN memory to produce an updated storage scoring resultant. The method continues with the processing module utilizing the updated storage scoring resultant to identify an updated set of storage units affiliated with a given storage pool of a plurality of storage pools of the DSN memory and sending at least one data migration request to at least one storage unit of the updated set of storage units regarding migration of at least one encoded data slice of the set of encoded data slices.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: October 15, 2019
    Assignee: PURE STORAGE, INC.
    Inventors: Jason K. Resch, Greg Dhuse, Manish Motwani, Andrew Baptist, Wesley Leggette
  • Patent number: 10440105
    Abstract: A method for utilizing a decentralized agreement protocol to rank storage locations in a dispersed storage network (DSN) for data access operations. In response to receiving a DSN access request including data for dispersed storage, a DSN address is determined based, at least in part, on the DSN access request. A storage unit pool including a plurality of storage units is identified, and a resource level selection approach is determined with respect to the storage unit pool. The method continues with requesting and obtaining ranked scoring information for the plurality of storage units in accordance with the resource level selection approach. Based on the ranked scoring information and the resource level selection approach, an information dispersal algorithm (IDA) width number of storage units of the storage unit pool are selected for storage of the data as encoded by the IDA into encoded data slices.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: October 8, 2019
    Assignee: PURE STORAGE, INC.
    Inventors: Ravi V. Khadiwala, Jason K. Resch, Wesley B. Leggette
  • Patent number: 10437733
    Abstract: An apparatus and method for efficient guest EPT manipulation. For example, one embodiment of a apparatus comprises: a hypervisor to create extended page table (EPT) mappings between a guest physical address (GPA) space and a host physical address (HPA) space; the hypervisor to create an EPT edit table and populate the EPT edit table with information related to permitted mappings between the GPA space and HPA space; a guest to read the EPT edit table to determine information related to the permitted mappings between the GPA space and HPA space, the guest to use the information to map one or more pages in the GPA space to one or more pages in the HPA space.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventor: Krystof C. Zmudzinski