Abstract: Memory reclamation is tailored to avoid certain synchronization instructions, speeding concurrent garbage collection while preserving data integrity and availability. Garbage collection reclaims objects no longer in use, or other unused areas of memory. Pointers are partitioned into address portions holding address values and garbage collection portions having a special bit. Marking code writes only the garbage collection portions, setting the special bit as a mark reference, relocation candidate, etc. Mutator threads may concurrently mutate the entire pointer to update the address, but mutation does not cause incorrect reclamations or failure to do other operations such as relocation. Meanwhile, execution speed is increased by avoiding CAS (compare-and-swap instructions or compare-and-set) synchronization instructions in the garbage collector. Non-CAS yet nonetheless atomic writes are used instead. Mutators run in user or kernel address spaces.

Abstract: A backup storage includes a persistent storage and a backup manager. The persistent storage stores virtual machine level backups and application level backups. The backup manager obtains a request for a point in time restoration of an application; identifies, based on the application, a virtual machine level backup of the virtual machine level backups that is associated with: a virtual machine that hosted an instance of the application and a first point in time prior to a restoration point in time specified by the request for the point in time restoration; identifies, based on the application, an application level backup of the application level backups that is associated with the restoration point in time; generates a point in time backup using: the identified virtual machine level backup, and the identified application level backup; and services the request using the point in time backup.

Abstract: Systems and methods (including hardware and software) are disclosed for us in a multi-core, multi-socket server with many RDMA network adapters and NVME solid state drives. One of the features of the subject matter is to optimize the total IO throughput of the system by first replacing software locks with non-interruptible event handlers running on specific CPU cores that own individual software data structures and hardware queues, and second by moving work to that CPU affinity without stalling due to software lock overhead.

Abstract: A method for migration of data is provided. The method includes triggering a rebuild of data according to a first migration mechanism from a first storage drive to a second storage drive. Monitoring space utilization associated with the second storage drive, and adaptively switching the migration of the data from the first migration mechanism to a second migration mechanism based on the monitoring.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.

Abstract: A method for accessing a flash memory device and a flash memory device. After receiving a write request for an address, a flash memory controller obtains an indicator of the address, where the indicator indicates a last access type of the address, which might be a write operation or a read operation. When determining the indicator indicates a write operation, which means the access type for the address is normally write operation, to save time, the flash memory controller perform a fast-write operation on the address, when the indicator indicates a read operation, which means there might be plenty of read operations on the address, to facilitate future read operation, the controller performs a slow-write operation on the address.

Abstract: An application server predicts respiratory disease risk, rescue medication usage, exacerbation, and healthcare utilization using trained predictive models. The application server includes model modules and submodel modules, which communicate with a database server, data sources, and client devices. The submodel modules train submodels by determining submodel coefficients based on training data from the database server. The submodel modules further determine statistical analysis data and estimates for medication usage events, healthcare utilization, and other related events. The model modules combine submodels to predict respiratory disease risk, exacerbation, rescue medication usage, healthcare utilization, and other related information. Model outputs are provided to users, including patients, providers, healthcare companies, electronic health record systems, real estate companies and other interested parties.

Abstract: Embodiments of the present invention are directed to facilitating concurrent forecasting associating with multiple time series data sets. In accordance with aspects of the present disclosure, a request to perform a predictive analysis in association with multiple time series data sets is received. Thereafter, the request is parsed to identify each of the time series data sets to use in predictive analysis. For each time series data set, an object is initiated to perform the predictive analysis for the corresponding time series data set. Generally, the predictive analysis predicts expected outcomes based on the corresponding time series data set. Each object is concurrently executed to generate expected outcomes associated with the corresponding time series data set, and the expected outcomes associated with each of the corresponding time series data sets are provided for display.

Abstract: A storage control unit which processes an I/O request from a host apparatus is provided in the storage apparatus and the storage control unit creates a host group by mapping same to each supported OS type and configures a function according to the corresponding OS type for each of the host groups, creates a first volume on the storage apparatus and creates a second volume to which a physical storage area is dynamically allocated from a storage device, according to a volume creation instruction, and the storage control unit creates, according to an instruction to create a volume path from the first volume to the second volume, a volume path which passes through a third volume which is interposed between the first volume and second volume and has been allocated to the host group according to the OS type of the host apparatus provided by the first volume.

Abstract: A memory system includes: a memory device; a valid page counter for counting the number of valid pages of each closed block in the memory device before and after a map update operation; a maximum valid page decrease amount detector for detecting a maximum valid page decrease amount by calculating a valid page decrease amount for each closed memory block based on the number of the valid pages for the corresponding closed memory block, so as to calculate a total sum of valid page decrease amounts; and a garbage collector for performing a garbage collection operation on a victim block in the memory device, when the number of free blocks in the memory device is less than a first threshold value and greater than a second threshold value and a ratio of the maximal valid page decrease amount to the total sum of the valid page decrease amounts is a third threshold value or less.

Abstract: A processor comprising a mode indicator, a plurality of processing cores, and a neural network unit (NNU), comprising a memory array, an array of neural processing units (NPU), cache control logic, and selection logic that selectively couples the plurality of NPUs and the cache control logic to the memory array. When the mode indicator indicates a first mode, the selection logic enables the plurality of NPUs to read neural network weights from the memory array to perform computations using the weights. When the mode indicator indicates a second mode, the selection logic enables the plurality of processing cores to access the memory array through the cache control logic as a cache memory.

Abstract: Embodiments of a distributed caching system are disclosed that cache data across multiple computing devices on a network. In one embodiment, a first caching system serves as a caching front-end to a distributed cluster of additional caching systems. The caching systems may be spread over multiple partition groups. In one embodiment, cache writes at a cache system in one partition group are distributed to other partition groups. By propagating the cache writes across multiple partition groups, the caches at the different partition groups include more recently accessed data, thereby increasing the likelihood of cache hits.

Abstract: A page is loaded into memory of an in-memory database system. Thereafter, it is determined whether to reorganized the page based on how such page is used. Based on such determination, the page is either reorganized by filling any free space gaps in memory and then, use of the reorganized page is enabled or, otherwise, use of the page is enabled without reorganization.

Abstract: Allocation of an entry in a variable size entry container is initiated in an in-memory database system. The variable size entry container includes a plurality of pages forming a chain. Thereafter, it is determined whether free space is found within the pre-existing pages. If free space is found, the entry is allocated in the free space. Otherwise, a new page is created and appended to the chain so that the entry can be allocated on such new page.

Abstract: Methods and systems for releasing space on a secondary storage device for resynchronization are provided. A system for releasing space on a secondary storage device for resynchronization includes a suspension detection module that determines that the relationship between a primary computing device and a secondary computing device is suspended. The system also includes a relationship resumption module that determines that the relationship between the primary computing device and a secondary computing device is resumed. The system further includes an extent release module that directs the secondary computing device to release extents in a secondary storage device of the secondary computing device that correspond to free extents in a primary storage device of the primary computing device. Additionally, the system includes a synchronization module that synchronizes data stored on the secondary storage device and the primary storage device.

Abstract: Embodiments for providing continuous data protection in a data processing and storage system with a storage server and storage devices, by providing a solid state disk (SSD) device having a processor and non-volatile memory and an interface to a host device, providing a resident continuous data protection program on the SSD and executed by the processor, recording, for each write command, a memory address offset and a timestamp for the write command, and maintaining one of: an undo journal storing data in a location that is to be overwritten by the write command with the timestamp, or a log-structured file exposing a single large file as a volume to an upper layer of a host software stack for storing periodic snapshot backups of data created by the write command.

Abstract: An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.

Abstract: Disclosed herein are techniques for implementing hybrid memory modules with improved inter-memory data transmission paths. The claimed embodiments address the problem of implementing a hybrid memory module that exhibits improved transmission latencies and power consumption when transmitting data between DRAM devices and NVM devices (e.g., flash devices) during data backup and data restore operations. Some embodiments are directed to approaches for providing a direct data transmission path coupling a non-volatile memory controller and the DRAM devices to transmit data between the DRAM devices and the flash devices. In one or more embodiments, the DRAM devices can be port switched devices, with a first port coupled to the data buffers and a second port coupled to the direct data transmission path. Further, in one or more embodiments, such data buffers can be disabled when transmitting data between the DRAM devices and the flash devices.

Abstract: In some examples of the disclosure, a parameter override mechanism may include a variable length configuration data table with entries for specific models of memory devices. The configuration data table entries may include override parameters for different memory devices and may be dynamically updated with new entries and modifications of existing entries. The parameter override mechanism may be configured to automatically detect a model of memory device and select a corresponding configuration data table entry based on the detected model of memory device or restrict the use of a configuration data table entry based on the detected model of memory device.

Abstract: Apparatus, method, and system for enhancing data prefetching based on non-uniform memory access (NUMA) characteristics are described herein. An apparatus embodiment includes a system memory, a cache, and a prefetcher. The system memory includes multiple memory regions, at least some of which are associated with different NUMA characteristic (access latency, bandwidth, etc.) than others. Each region is associated with its own set of prefetch parameters that are set in accordance to their respective NUMA characteristics. The prefetcher monitors data accesses to the cache and generates one or more prefetch requests to fetch data from the system memory to the cache based on the monitored data accesses and the set of prefetch parameters associated with the memory region from which data is to be fetched. The set of prefetcher parameters may include prefetch distance, training-to-stable threshold, and throttle threshold.