Patents Examined by Tracy C Chan
  • Patent number: 11023808
    Abstract: A system to detect a feature in an input image comprising a processor to evaluate a model including: four layers including: a supragranular layer, a granular layer, a first infragranular layer, and a second infragranular layer, each of the layers including a base connection structure including: an excitatory layer including a excitatory neurons arranged in a two dimensional grid; and an inhibitory layer including a inhibitory neurons arranged in a two dimensional grid; within-layer connections between the neurons of each layer in accordance with a Gaussian distribution; between-layer connections between the neurons of different layers, the probability of a neuron of a first layer of the different layers to a neuron of a second layer of the different layers in accordance with a uniform distribution; and input connections from lateral geniculate nucleus (LGN) neurons of an input LGN layer to the granular layer in accordance with a uniform distribution.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: June 1, 2021
    Assignee: HRL Laboratories, LLC
    Inventors: Qin Jiang, Narayan Srinivasa
  • Patent number: 11010088
    Abstract: The Dynamically Determined Difference Regions Apparatuses, Methods and Systems (“DDDR”) transforms backup configuration request, backup data read response inputs via DDDR components into backup configuration response, changed blocks update request outputs. A write command for a data block to write to a data volume is detected. A data volume address of the data block is determined. A superset range associated with the data volume address is determined. Upon determining that the written-to flag of the superset range is set: extend a previously established written-to subset range within the superset range to include the data volume address when it is determined that the data volume address is not within the previously established written-to subset range. Upon determining that the written-to flag is not set: set the written-to flag and establish a new written-to subset range within the superset range that includes the data volume address. Execute the write command.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: May 18, 2021
    Assignee: Datto, Inc
    Inventors: Robert Loce, Stuart Mark
  • Patent number: 11010079
    Abstract: Examples relate to a controller apparatus or controller device for a solid-stage storage device, to an apparatus or device for a host computer, to corresponding methods and computer programs, to a solid-stage storage device and to a host computer comprising a solid-state storage device. Examples provide a controller apparatus for a solid-state storage device. The solid-state storage device comprises non-volatile buffer memory circuitry and storage circuitry. The controller apparatus comprises interface circuitry for communicating with a host computer. The controller apparatus comprises processing circuitry configured to obtain a control instruction related to a file system of a partition from the host computer. The partition is at least partially stored within the storage circuitry of the solid-state storage device. The control instruction indicates a location of file system metadata within the partition.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventor: Peng Li
  • Patent number: 10983715
    Abstract: The present disclosure describes technologies and techniques for use by a data storage controller—such as a controller for use with a NAND or other non-volatile memory (NVM)—to provide a user-expandable memory space. In examples described herein, a customer may choose to purchase access to only a portion of the total available memory space of a consumer device, such as a smartphone. Later, the customer may expand the user-accessible memory space. In one example, the customer submits suitable payment via a communication network to a centralized authorization server, which returns an unlock key. Components within the data storage controller of the consumer device then use the key to unlock additional memory space within the device. In this manner, if the initial amount of memory the consumer paid for becomes full, the consumer may conveniently expand the amount of user-accessible memory.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: April 20, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Liran Sharoni, Amir Shaharabany
  • Patent number: 10969973
    Abstract: Techniques of implementing software filtered non-volatile memory in a computing device are disclosed herein. In one embodiment, a method includes detecting an entry being written to a guest admin submission queue (gASQ) by a memory driver of a virtual machine hosted on the computing device. Upon detecting the entry written to the gASQ by the memory driver, the command in the entry is analyzed to determine whether the command is allowed based on a list of allowed or disallowed commands. In response to determining that the command in the entry is not allowed, without sending the command to the non-volatile memory, generating an execution result of the command in response to the entry being written to the gASQ by the memory driver. As such, potentially harmful commands from the memory driver are prevented from being executed by the non-volatile memory.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: April 6, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Martijn de Kort, David Hepkin, Murtaza Ghiya, Liang Yang, Matthew David Kurjanowicz
  • Patent number: 10949110
    Abstract: Apparatus and method for managing metadata in a data storage device, such as a solid-state drive (SSD). In some embodiments, a non-volatile memory (NVM) includes a population of semiconductor memory dies. The dies are connected a number of parallel channels such that less than all of the semiconductor dies are connected to each channel. A controller circuit apportions the semiconductor memory dies into a plurality of die sets, with each die set configured to store user data blocks associated with a different user. The controller circuit subsequently rearranges the dies into a different arrangement of die sets so that at least one die is migrated from a first dies set to a second die set. A map manager circuit is configured to establish an array of pointers in a memory to identify contiguous portions of map metadtata that describe user data stored in the at least one migrated die.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 16, 2021
    Assignee: Seagate Technology LLC
    Inventors: Stacey Secatch, David W. Claude, Steven S. Williams, Jeff Rogers
  • Patent number: 10942864
    Abstract: Examples herein involve processing data in a distributed data processing system using an off-heap memory store. An example involves allocating a shared memory region of a shared memory to store attributes corresponding to a first partition of a distributed data system, and updating, in the shared memory region, the attributes corresponding to updates to the local data from process iterations of the first partition, such that a second partition of the distributed data system has access to the updated attributes.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: March 9, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Mijung Kim, Alexander Ulanov, Jun Li
  • Patent number: 10936245
    Abstract: A storage device includes a memory device and a controller. The memory device stores attribute information associated with a host memory buffer allocated on a host memory. The controller communicates with the host memory such that a plurality of pieces of data associated with operations of the memory device is buffered, based on the attribute information, in a plurality of host memory buffers allocated on the host memory. The controller communicates with the host memory such that first data corresponding to a first attribute group managed in the attribute information is buffered in a first host memory buffer among the plurality of host memory buffers and second data corresponding to a second attribute group different from the first attribute group is buffered in a second host memory buffer separate from the first host memory buffer.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: March 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jison Im, Hyunseok Kim, Hyun-Sik Yun, Hoju Jung
  • Patent number: 10884642
    Abstract: A method for performing data-accessing management in a storage server and associated apparatus such as a host device, a storage device, etc. are provided. The method includes: in response to a client request of writing a first set of data into the storage server, utilizing the host device within the storage server to trigger broadcasting an internal request corresponding to the client request toward each storage device of a plurality of storage devices within the storage server; and in response to the internal request corresponding to the client request, utilizing said each storage device of the plurality of storage devices to search for the first set of data in said each storage device to determine whether the first set of data has been stored in any storage device, for controlling the storage server completing the client request without duplication of the first set of data within the storage server.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: January 5, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Wen-Long Wang
  • Patent number: 10884639
    Abstract: Aspects of the disclosure are directed to providing a single data rate (SDR) mode or a double data rate (DDR) mode to a Registering Clock Drive (RCD) for a memory. Accordingly, the apparatus and method may include determining data rate mode selection criteria; selecting a data rate mode based on the data rate mode selection criteria; configuring a host interface for the data rate mode; and configuring an RCD input interface for the data rate mode. In one aspect, the apparatus and method further include activating a clock signal on the host interface and on the RCD input interface; transferring data from the host interface to the RCD input interface using the clock signal; and transferring the data from an RCD output interface using the clock signal in either 1N mode or 2N mode. And, the data rate mode is one of the SDR mode or the DDR mode.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: January 5, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Liyong Wang, Kuljit Singh Bains, Wesley Queen
  • Patent number: 10877688
    Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: December 29, 2020
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Peter F. Holland, Erik P. Machnicki, Robert E. Jeter, Rakesh L. Notani, Neeraj Parik, Marc A. Schaub
  • Patent number: 10877699
    Abstract: Destaging data from a first tier data store to a second tier data store can be performed periodically and concurrently while processing user I/O operations. Each round of destaging can be delayed by certain amount (sleep time). A throttling factor can be used to compute the sleep time as a fraction of a base sleep time. The throttling factor can vary based on the usage level of first tier data store, and can be used to determine the destage frequency.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: December 29, 2020
    Assignee: VMware, Inc.
    Inventors: Aditya Kotwal, Christian Dickmann
  • Patent number: 10877888
    Abstract: Systems, apparatuses, and methods for implementing a distributed global ordering point are disclosed. A system includes at least a communication fabric, sequencing logic, and a plurality of coherence point pipelines. Each coherence point pipeline receives transactions from the communication fabric and then performs coherence operations and a memory cache lookup for the received transactions. The global ordering point of the system is distributed across the outputs of the separate coherence point pipelines. Device-ordered transactions travelling upstream toward memory are assigned sequence numbers by the sequencing logic. The transactions are speculatively issued from the communication fabric to the coherence point pipelines. Speculatively issuing the transactions to the coherence point pipelines may cause the transactions to pass through the distributed global ordering point out of order. Control logic on the downstream path reorders the transactions based on the assigned sequence numbers.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: December 29, 2020
    Assignee: Apple Inc.
    Inventors: Harshavardhan Kaushikkar, Sridhar Kotha, Srinivasa Rangan Sridharan, Xiaoming Wang, Yu Zhang
  • Patent number: 10866742
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for archiving storage volume snapshots. An archive module determines at least one snapshot or point in time copy of data. A metadata module determines metadata for restoring a snapshot or point in time copy. A storage module replicates a snapshot or point in time copy and stores the replicated snapshot or point in time copy and metadata to a target storage location, such as one or more data files in a file system of one or more storage devices from a different vendor than a storage device from which the data was copied. In another embodiment, both the ability to archive a storage volume snapshot and restore a previously archived storage volume snapshot is provided.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: December 15, 2020
    Assignee: NEXGEN STORAGE, INC.
    Inventors: John A. Patterson, Sebastian P. Sobolewski
  • Patent number: 10860235
    Abstract: The first to third storage apparatuses each comprise an SVOL1, SVOL2 and PVOL. Even when the write command designates any of the PVOL, SVOL1 and SVOL2, at least one of the first to third storage apparatuses writes write target data according to the write command to the PVOL and then writes the write target data in parallel to the SVOL1 and SVOL2. Even if a read command designates any of the PVOL, SVOL1 and SVOL2, at least one of the first to third storage apparatuses reads read target data according to the read command from the PVOL.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: December 8, 2020
    Assignee: HITACHI, LTD.
    Inventors: Koki Matsushita, Toru Suzuki, Takahito Sato, Atsushi Oku
  • Patent number: 10860962
    Abstract: A system for fully integrated collection of business impacting data, analysis of that data and generation of both analysis driven business decisions and analysis driven simulations of alternate candidate business action comprising a business data retrieval engine stored in a memory of and operating on a processor of a computing device, a business data analysis engine stored in a memory of and operating on a processor of a computing device and a business decision and business action path simulation engine stored in a memory of and operating on a processor of one of more computing devices has been developed.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: December 8, 2020
    Assignee: QOMPLX, INC.
    Inventors: Jason Crabtree, Andrew Sellers
  • Patent number: 10860219
    Abstract: Data is copied, from a second group of data blocks in a second plurality of groups of data blocks that are mapped, to a first group of data blocks in a first set of groups of data blocks that are not mapped to include the first group of data blocks in the second set of groups of data blocks that are mapped. A sub-total write counter associated with the first group of data blocks is reset. A value of the sub-total write counter indicates a number of write operations performed on the first group of data blocks since the first group of data blocks has been included in the second set of groups of data blocks. A wear leveling operation is performed on the first group of data blocks based on the sub-total write counter.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fangfang Zhu, Jiangli Zhu, Ning Chen, Ying Yu Tai
  • Patent number: 10831371
    Abstract: Embodiments of systems and methods are provided for data storage in a tiered storage system comprising at least two storage tiers. A method comprises: providing storage information for each storage tier of the storage tiers to a user. The storage information comprising values of storage parameters, wherein the storage parameters comprise at least one of a storage quota limit of the user, usable storage capacity in the tier for the user based on the storage quota limit, and consumed storage capacity of the tier by the user. The storage information is used to move data between the storage tiers.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dominic Mueller-Wicke, Nils Haustein
  • Patent number: 10831403
    Abstract: Embodiments described herein are operable in a computing system. The computing system receives first and second commands (e.g., I/O commands). The computing system determines that the first command has a higher priority than the second I/O command, and queues the second command for servicing at a later time. The computing system services the first command, and services the second command after a timeout period based on performance degradation limit that decreases command processing performance of the computing system, overrides the timeout period, and increases a probability of executing the second command.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: November 10, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jeffrey V. DeRosa, Ling Zhi Yang, Kenneth L. Barham, Mark A. Gaertner
  • Patent number: 10817209
    Abstract: Provided is a storage controller that reduces a reference number to duplicate data even if there is duplicate data. The storage controller includes a memory and processor and is connected to a server and physical storage device. The memory stores a VOL management table, an address translation table, and a generation management table; registers a first provision volume and a first additional writing volume in the VOL management table; registers a reference destination of a first address of the first provision volume as a second address of the first additional writing volume in the address translation table. The processor receives a request for replication of the first provision volume; registers the second provision volume and the third provision volume in the generation management table as the child generation of the first provision volume; and processes the request to the first provision volume as a request to the third provision volume.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: October 27, 2020
    Assignee: HITACHI, LTD.
    Inventors: Takaki Matsushita, Tomohiro Kawaguchi, Kazuei Hironaka