Abstract: Provided is a light emitting device which includes a light emitting element having a peak emission wavelength in a range of 400 nm to 500 nm, and a fluorescent member containing a fluorescent material having a peak emission wavelength in a range of 630 nm to 670 nm, and a composition represented by the formula. CasSrtEuuSivAlwNx. In the formula, s, t, u, v, w, and x satisfy 0.25?s?0.5, 0.4?t?0.75, 0.01?u?0.04, 0.8?s+t+u?1.1, 0.8?v?1.2, 0.8?w?1.2, 1.8?v+w?2.2, and 2.5?x?3.2. The light emitting device emits light having an x value of CIE 1931 chromaticity coordinates of 0.640 or more.

Abstract: A display apparatus includes a display panel, a driver, a controller and a first flexible substrate. The display panel includes first and second substrates facing each other. The first substrate includes a switching element connected to a pixel electrode. The driver provides a driving signal to the display panel. The controller provides a control signal to the driver. The controller includes first and second printed circuit boards spaced apart from each other. The first flexible substrate electrically connects the first and second printed circuit boards to each other. The first flexible substrate defines a first contact portion at which the first flexible substrate is connected to the first printed circuit board, a second contact portion at which the first flexible substrate is connected to the second printed circuit board, and an overlap portion overlapping the display panel and at which the first flexible substrate is attached to the display panel.

Abstract: A semiconductor device includes a first electrode, a second electrode, a semiconductor element, an insulating layer and a third electrode. The semiconductor element is electrically connected to the first electrode and the second electrode. The third electrode is insulated from the semiconductor structure, the first electrode and the second electrode through the insulating layer. The semiconductor element includes a semiconductor structure, a carbon nanotube and a conductive film. The semiconductor structure includes a P-type semiconductor layer and an N-type semiconductor layer and defines a first surface and a second surface. The carbon nanotube is located on the first surface of the semiconductor. The conductive film is located on the second surface of the semiconductor. The conductive film is formed on the second surface by a depositing method or a coating method.

Abstract: The present disclosure is related to an optoelectronic device comprising a semiconductor stack comprising a first surface and a second surface opposite to the first surface; a first contact layer on the first surface; and a second contact layer on the second surface, wherein the second contact layer is not overlapped with the first contact layer in a vertical direction; wherein the second contact layer comprises a plurality of dots separating from each other and formed of semiconductor material.

Abstract: A semiconductor structure includes a semiconductor layer, a carbon nanotube and a conductive film. The semiconductor layer includes a first surface and a second surface. A thickness of the semiconductor layer ranges from 1 nanometer to 100 nanometers. The carbon nanotube is located on the first surface of the semiconductor. The conductive film is located on the second surface of the semiconductor. The conductive film is formed on the second surface by a depositing method. The carbon nanotube, the semiconductor layer and the conductive film are stacked with each other to form a three-layered stereoscopic structure.

Abstract: Provided are quantum dots passivated by oligomers or polymers which are formed by a reaction of a first monomer having at least three thiol groups (—SH) at the terminal end with a second monomer having at least two functional groups at the terminal end that can react with the thiol groups, and a spacer group between the at least two functional groups.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to variable space mandrel cut for self-aligned double patterning and methods of manufacture. The method includes: forming a plurality of mandrels on a substrate; forming spacers about the plurality of mandrels and exposed portions of the substrate; removing a portion of at least one of the plurality of mandrels to form an opening; and filling in the opening with material.

Abstract: An image sensor including first and second pixel regions adjacent to each other in a first direction in a light-receiving region that receives light and generates charges; a third pixel region adjacent to the first pixel region in a second direction intersecting the first direction in the light-receiving region; a first device isolation layer between the first and second pixel regions and between the first and third pixel regions to separate the first pixel region from the second pixel region and the first pixel region from the third pixel region; second device isolation layers in each of the first to third pixel regions to define active regions; a plurality of transfer gates and a plurality of logic gates on the active regions; and a side connection contact overlapping the first device isolation layer and connected to a side surface of an active region.

Abstract: A component to be transferred to a receiving substrate is to be coupled both electrically and thermally. This is achieved by an integrated circuit comprising a substrate and a plurality of first components formed in or on the substrate. A plurality of metallization layers are provided. A second component applied by transfer printing is provided which is positioned, at least in part, on a level with and laterally adjacent to at least one of the plurality of metallization layers.

Abstract: Semiconductor device structures with reduced gate end width formed at gate structures and methods for manufacturing the same are provided. In one example, a semiconductor device structure includes a plurality of gate structures formed over a plurality of fin structures, the gate structures formed substantially orthogonal to the fin structures, wherein the plurality of gate structures includes a first gate structure having a first gate end width and a second gate structure having a second gate end width, wherein the second gate end width is shorter than the first gate end width.

Abstract: A method of manufacturing a package which comprises encapsulating at least part of an electronic chip by an encapsulant, subsequently covering a part of the electronic chip with a chip attach medium, and attaching the encapsulated electronic chip on a chip carrier via the chip attach medium.

Abstract: A semiconductor test system has a film frame including a tape portion with one or more openings through the tape portion. The opening is disposed in a center region of the tape portion of the film frame. The film frame may have conductive traces formed on or through the tape portion. A thin semiconductor wafer includes a conductive layer formed over a surface of the semiconductor wafer. The semiconductor wafer is mounted over the opening in the tape portion of the film frame. A wafer probe chuck includes a lower surface and raised surface. The film frame is mounted to the wafer probe chuck with the raised surface extending through the opening in the tape portion to contact the conductive layer of the semiconductor wafer. The semiconductor wafer is probe tested through the opening in the tape portion of the film frame.

Abstract: A device includes a first vertical nanowire, a second vertical nanowire and a gate. The first vertical nanowire is disposed on a substrate, wherein the first vertical nanowire includes a silicon germanium channel part. The second vertical nanowire is disposed on the substrate beside the first vertical nanowire, wherein the second vertical nanowire includes a silicon channel part. The gate encircles the silicon germanium channel part and the silicon channel part. The present invention provides a method of forming said device including the following steps. A substrate is provided. A silicon vertical nanowire is formed on the substrate. A germanium containing layer is formed on sidewalls of the silicon vertical nanowire. Germanium atoms of the germanium containing layer are driven into the silicon vertical nanowire, thereby forming a silicon germanium channel part of the silicon vertical nanowire. A gate encircling the silicon germanium channel part is formed.

Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first stack in a first device region, the first stack including layers of a first channel material and layers of a sacrificial material. A second stack is formed in a second device region, the second stack including layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material. The sacrificial material is etched away using a wet etch that is selective to the sacrificial material and the second channel material and does not affect the first channel material or the liner. The liner protects the second channel material from the wet etch.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate having a front side and a back side and a pixel region having a plurality of pixels in the front side, each pixel including a sensor element, forming a metal reflective layer in the front side of the substrate and on the pixel region, thinning the back side of the substrate, doping the thinned back side of the substrate with a dopant, and laser annealing the doped back side of the substrate. The sensor element is configured to receive incident light to the thinned back side of the semiconductor substrate. The metal reflective layer reflects heat generated in the laser annealing process to more fully activate the dopant in the back side of the substrate, thereby effectively reducing dark current and improving the device performance.

Abstract: A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode located above the semiconductor substrate; a sense anode electrode located above the semiconductor substrate; a first resistance layer located above the semiconductor substrate, having resistivity higher than resistivities of the upper main electrode and the sense anode electrode, and connecting the upper main electrode and the sense anode electrode; and a lower main electrode located below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode includes a p-type first anode region connected to the sense anode electrode and an n-type first cathode region connected to the lower main electrode.

Abstract: A thin film transistor (TFT) array substrate structure based on organic light-emitting diodes (OLEDs) may include multiple sets of TFT components, capacitors, common electrodes, and data signal lines, all of which are formed on a substrate. Each set of TFT components includes a driving TFT, and the driving TFT has a gate, a source, and a drain. A drain frame extends from the drain and surrounds a pixel block of the TFT array substrate structure, and a transparent conductive film is arranged in a region surrounded by the drain frame and is in contact with the drain frame.

Abstract: Methods of forming a buffer layer to imprint ferroelectric phase in a ferroelectric layer and the resulting devices are provided. Embodiments include forming a substrate; forming a buffer layer over the substrate; forming a ferroelectric layer over the buffer layer; forming a channel layer over the ferroelectric layer; forming a gate oxide layer over a portion of the channel layer; and forming a gate over the gate oxide layer.

Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.

Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.