Abstract: According to one embodiment, a forming method of superposition checking marks includes forming a first superposition checking mark to have a first step with respect to an arrangement surface for the first superposition checking mark, forming an opaque film having a second step resulting from the first step on the arrangement surface, and forming on the opaque film a second superposition checking mark provided with a transparent film allowing observation of the second step.

Abstract: Provided herein are nanostructure networks having high energy storage, electrochemically active electrode materials including nanostructure networks having high energy storage, as well as electrodes and batteries including the nanostructure networks having high energy storage. According to various implementations, the nanostructure networks have high energy density as well as long cycle life. In some implementations, the nanostructure networks include a conductive network embedded with electrochemically active material. In some implementations, silicon is used as the electrochemically active material. The conductive network may be a metal network such as a copper nanostructure network. Methods of manufacturing the nanostructure networks and electrodes are provided. In some implementations, metal nanostructures can be synthesized in a solution that contains silicon powder to make a composite network structure that contains both.

Abstract: An optoelectronic component includes a composite body including a molded body; and an optoelectronic semiconductor chip embedded into the molded body, wherein the optoelectronic semiconductor chip includes a first electrical contact on its top side, a first top side metallization is arranged on the top side of the composite body and electrically conductively connects the first electrical contact to the through contact, a second top side metallization is arranged on the top side of the composite body and electrically insulated with respect to the first top side metallization, the second top side metallization completely delimits a part of the top side of the optoelectronic semiconductor chip, and a wavelength-converting material is arranged in a region completely delimited by the second top side metallization on the top side of the composite body, the wavelength-converting material extending as far as the second top side metallization.

Abstract: A coated substrate may provide soft touch and superhydrophobicity. In example implementations herein, a substrate may be provided with a microstructure on at least a portion of at least one surface of the substrate. A first, water-based soft touch coating may be on at least a portion of the microstructure. A second, solvent-based superhydrophobic coating may be on at least a portion of the first coating.

Abstract: A semiconductor device package includes an electronic component and an electrical interconnect. The electronic component is attached to the electrical interconnect. The electrical interconnect is configured to electrically couple the electronic component to external terminals of the semiconductor device package. The electrical interconnect has a first main face facing the electronic component and a second main face opposite the first main face. The semiconductor device package further includes a first semiconductor chip facing the second main face of the electrical interconnect.

Abstract: Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

Abstract: The invention relates to a semiconductor structure intended to receive an electromagnetic wave. The semiconductor structure comprises at least one first semiconductor resonant optical cavity conformed to absorb at least partially the electromagnetic wave and to provide an electrical signal proportional to the part of the electromagnetic wave absorbed. The semiconductor structure further includes a second dielectric resonant optical cavity of which a resonance wavelength is comprised in the predetermined range of wavelengths and is preferentially equal to the wavelength ?0, the second resonant optical cavity being laid out to intercept at least part of the electromagnetic wave and being optically coupled to the first resonant optical cavity. The second resonant optical cavity is transparent to the predetermined range of wavelengths. The invention further relates to a semiconductor component comprising such a semiconductor structure and a method of manufacturing such a semiconductor structure.

Abstract: Provided is a wafer-level package with metal shielding structure and the manufacturing method for producing the same. The wafer-level package includes first conductive structures for securing a die unit to a substrate, and is featured by disposing one or more second conductive structures that are located at the front surface of the die unit and proximate to a side surface of the die unit. The second conductive structure does not electrically connected to the internal circuitry of the die unit. After the wafer is cut, a metal shielding layer is formed on the back surface and the side surfaces of the die unit. Afterwards, the die unit is mounted on the substrate to allow the second conductive structure to connect to the ground structure on the substrate and connect to the metal shielding layer. Thus, EMI shielding function is generated to efficiently suppress EMI and miniaturize the package.

Abstract: A semiconductor device includes an oxide semiconductor layer, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first barrier layer below the oxide semiconductor layer, and a second barrier layer above the oxide semiconductor layer, the second barrier layer covering a top surface and side surfaces of the oxide semiconductor layer and being in contact with the first barrier layer in a region around the oxide semiconductor layer.

Abstract: A light-emitting device is provided, including: a substrate; a reflective layer disposed on the substrate; a patterned contact layer disposed on the reflective layer; a light-emitting unit disposed on the patterned contact layer; a first electrode disposed on a top surface of the light-emitting unit; and a second electrode disposed on a bottom surface of the light-emitting unit; wherein a projection of the first electrode on the substrate and a projection of the patterned contact layer on the substrate are complementary to each other.

Abstract: A semiconductor device includes a substrate, a memory structure and a capacitor structure including at least one array of capacitors. The memory structure is disposed in a first region of the device. The capacitor structure is disposed in a second region of the device. The capacitor structure may include a first capacitor array, a second capacitor array, a third capacitor array and a first landing pad. The first landing pad is disposed between the substrate and lower electrodes of capacitors of the first and second capacitor arrays, and contacts the lower electrodes so as to electrically connect the first capacitor array and the second capacitor array. Upper electrodes of capacitors of the second and third capacitor arrays are integral such that the second capacitor array and the third capacitor array are electrically connected to each other.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a source layer; removing part of the source layer to form a first opening; forming a first channel layer in the first opening; forming a gate layer around the first channel layer and on the source layer; forming a drain layer on the gate layer and the first channel layer; removing part of the drain layer to form a second opening; and forming a second channel layer in the second opening.

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a front side and back side opposing the front side, the integrated circuit structure comprising: a through-silicon-via (TSV) at least partially within a dielectric layer extending away from the front side; a first metal adjacent to the TSV and within the dielectric layer, the first metal being substantially surrounded by a first seed layer; a conductive pad over the first metal and the TSV and extending away from the front side, wherein the conductive pad provides electrical connection between the TSV and the first metal and includes a second seed layer substantially surrounding a second metal, wherein the second seed layer separates the second metal from the first metal and the TSV.

Abstract: Method for producing at least one electronic chip support, from a plate that includes a first face intended to be in contact with a chip reader, a second face, covered with a first layer of electrically conductive material and intended to be linked to a radio antenna, and a core made from an electrically insulating material separating the first face from the second face. This method includes steps of drilling at least one through hole through the plate, depositing a layer of electrically conductive material on the first face and chemically etching a first electric circuit and a second electric circuit on the first face and the second face respectively. Prior to the chemical etching step, a step of depositing a third layer of electrically conductive material in the hole or holes, which covers the electrically insulating material in the corresponding hole or holes.

Abstract: A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

Abstract: A semiconductor test system has a film frame including a tape portion with one or more openings through the tape portion. The opening is disposed in a center region of the tape portion of the film frame. The film frame may have conductive traces formed on or through the tape portion. A thin semiconductor wafer includes a conductive layer formed over a surface of the semiconductor wafer. The semiconductor wafer is mounted over the opening in the tape portion of the film frame. A wafer probe chuck includes a lower surface and raised surface. The film frame is mounted to the wafer probe chuck with the raised surface extending through the opening in the tape portion to contact the conductive layer of the semiconductor wafer. The semiconductor wafer is probe tested through the opening in the tape portion of the film frame.

Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate, having an emitter layer of a first conductivity type, a collector layer of a second conductivity type and a drift layer of the first conductivity type sandwiched therebetween, the emitter layer disposed at a front surface side of the semiconductor substrate and the collector layer disposed at a rear surface side of the semiconductor substrate, a base layer of the second conductivity type between the drift layer and the emitter layer, a buffer layer of the first conductivity type between the collector layer and the drift layer, the buffer layer having an impurity concentration higher than that of the drift layer, and having an impurity concentration profile with two peaks in regard to a depth direction from the rear surface of the semiconductor substrate, and a defect layer, formed in the drift layer and having an impurity concentration profile with a half-value width of not more than 2 ?m in regard to the depth direc

Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a handle layer. A partial buried insulator overlies the handle layer and underlies the active layer, terminates at a buried insulator termination point, and includes an electrically insulating material. A substrate extension is adjacent to the partial buried insulator, where the substrate extension overlies the handle layer and underlies the active layer, and where the substrate extension directly contacts the partial buried insulator at the buried insulator termination point. The substrate extension includes a semiconductive material. A memory gate overlies the active layer.