Abstract: A semiconductor device includes: a visible light sensing layer, having a first surface and a second surface opposite to the first surface; an infrared ray sensing layer, having a first surface and a second surface opposite to the first surface, and the first surface of the visible light sensing layer attached to the second surface of the infrared ray sensing layer; and a circuitry layer, having a first surface and a second surface opposite to the first surface, and the first surface of the infrared ray sensing layer attached to the second surface of the circuitry layer.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a through via extending through the semiconductor substrate from the first surface to the second surface, a metal layer adjacent an inside surface of the through via, and an insulating film including OH bonds located between the semiconductor substrate and the metal layer, the insulating film having a thickness of 1 ?m or less.

Abstract: A light-emitting device may include separate, first and second light-emitting structures that are isolated from direct contact with each other on a phototransmissive substrate. Each light-emitting structure may include a first conductivity-type semiconductor layer, an active layer on the first conductivity-type semiconductor layer, and a second conductivity-type semiconductor layer on the active layer. The first and second light-emitting structures may be electrically connected to each other. An inter-structure conductive layer may electrically interconnect the first conductivity-type semiconductor layer of the first light-emitting structure to the second conductivity-type semiconductor layer of the second light-emitting structure. The second light-emitting structure may include a finger structure extending from an outer edge of the second light-emitting structure toward an interior of the second light-emitting structure.

Abstract: A semiconductor device includes a plurality of cell gate electrodes on a semiconductor substrate. End portions of the cell gate electrodes include stepped-pad regions that extend in a direction parallel to a surface of the semiconductor substrate. Vertical structures are on the semiconductor substrate and pass through the plurality of cell gate electrodes. The vertical structures respectively include a channel layer. Upper peripheral transistors are disposed on the semiconductor substrate. The upper peripheral transistors include an upper peripheral gate electrode at a level higher than a level of the plurality of cell gate electrodes, body patterns passing through the upper peripheral gate electrode and electrically connected to the pad regions, and gate dielectric layers between the upper peripheral gate electrode and the body patterns.

Abstract: A disclosed compound semiconductor device includes a substrate, a channel layer formed over the substrate, an electron supply layer famed on the channel layer, a first cap layer and a second cap layer formed at a distance from each other on the electron supply layer, a source electrode formed on the first cap layer, a drain electrode formed on the second cap layer, and a gate electrode formed on the electron supply layer between the first cap layer and the second cap layer. Each of the first cap layer and the second cap layer is a stacked film formed by alternately stacking i-type first compound semiconductor layers and n-type second compound semiconductor layers having a wider bandgap than the first compound semiconductor layers.

Abstract: A quantum light emitting diode comprises a first electrode; a second electrode facing the first electrode; a light-amount enhancing layer between the first and second electrodes and having a structure guiding emitted light toward an emitting side; and an emitting material layer between the light-amount enhancing layer and the second electrode and including a quantum particle at the structure of the light-amount enhancing layer.

Abstract: A method for manufacturing embedded memory using high-?-metal-gate (HKMG) technology is provided. A gate stack is formed on a semiconductor substrate. The gate stack comprises a charge storage film and a control gate overlying the charge storage film. The control gate includes a first material. A gate layer is formed of the first material, and is formed covering the semiconductor substrate and the gate stack. The gate layer is recessed to below a top surface of the gate stack, and subsequently patterned to form a select gate bordering the control gate and to form a logic gate spaced from the select and control gates. An ILD layer is formed between the control, select, and logic gates, and with a top surface that is even with top surfaces of the control, select, and logic gates. The control, select, or logic gate is replaced with a new gate of a second material.

Abstract: A multi-chip module structure (MCM) having improved heat dissipation includes a plurality of semiconductor chips having a front side mounted on a packaging substrate, wherein each semiconductor chip of the plurality of semiconductor chips further includes a through-substrate vias located at a backside of each semiconductor chip of the plurality of semiconductor chips. A plurality of wire bonds is present that provides interconnect between each semiconductor chip of the plurality of semiconductor chips and is located at the backside of each semiconductor chip of the plurality of semiconductor chips. A heat sink is located above a gap containing the plurality of wire bonds, and a cooling element is located on a surface of the heat sink.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor substrate having a first wiring electrode on a first surface thereof, a first protective layer on the semiconductor substrate, having an opening therethrough at the location of first wiring electrode, a first bump electrode in the opening of the first protective layer, the first bump electrode including a base overlying the wiring electrode and an opposed bump receiving surface, and a first bump comprising a bump diameter of 30 ?m or less connected to the first bump electrode. The width of the base of the first bump electrode within the opening is equal to or less than 1.5 times the thickness of the first protective layer.

Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method entails: forming a dielectric layer on a semiconductor substrate; forming a functional layer on the dielectric layer; forming a hard mask layer on the functional layer; patterning the semiconductor substrate to form an opening on the semiconductor substrate, wherein the opening goes through the hard mask layer, the functional layer and extends into the dielectric layer; performing an oxidization process on side surfaces of the functional layer inside the opening to form oxide layers; performing a first process on the semiconductor substrate to remove a portion of the dielectric layer underneath the opening to expose the semiconductor substrate; and removing the oxide layers on the side surfaces of the functional layer to form a contact hole. The contact hole has a wider opening in the upper part than in the lower part.

Abstract: A display device may include a light shield layer on a first substrate; a buffer layer on the light shield layer; a semiconductor layer on the buffer layer; a first insulating layer on the semiconductor layer; a gate metal layer on the first insulating layer; a second insulating layer having a contact hole on the gate metal layer and exposing a portion of the gate metal layer; and a source drain metal layer on the second insulating layer and in contact with the gate metal layer through the contact hole, wherein the semiconductor layer includes an auxiliary contact hole located in an area corresponding to the contact hole.

Abstract: An image sensor configured to provide improved reliability may include a charge passivation layer that includes a multiple different elements, each element of the different elements being a metal element or a metalloid element. The different elements may include a first element of a first group of periodic table elements and a second element of a second, different group of periodic table elements. The charge passivation layer may include an amorphous crystal structure.

Abstract: The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.

Abstract: Provided is a light-emitting element package, one embodiment comprising: a substrate; a light-emitting element disposed on the substrate; and a molded part surrounding the side surfaces and the top surface of the light-emitting element and having patterns on a surface from which the light incident thereto from the light-emitting element is output, wherein a part of the patterns correspond to a first area corresponding to the light-emitting element, and to a second area around the first area and are arranged at an angular range of 120 to 130 degrees on the surface of the molded part.

Abstract: In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

Abstract: A semiconductor device includes a semiconductor substrate, a circuit unit and an align mark. The circuit unit is disposed on the semiconductor substrate. The align mark includes a first part and a second part respectively formed in the semiconductor substrate and adjacent to two opposite sides of the circuit unit, wherein the first part and the second part depart from each other for a predetermined distance along with a first direction.

Abstract: A thin film transistor array panel includes a substrate; a data line disposed on the substrate; a buffer layer disposed on the substrate and spaced apart from the data line in a plan view; a thin film transistor disposed on the buffer layer, the thin film transistor including an oxide semiconductor layer; and a pixel electrode connected to the thin film transistor.

Abstract: A display device is disclosed. In one aspect, the display device includes a substrate, a first signal line formed over the substrate and a first insulating layer formed over the substrate and the first signal line. The display device also includes a second signal line formed over the first insulating layer and including an overlapping area that overlaps the first signal line, a second insulating layer formed over the second signal line and having a via hole that exposes at least a part of the overlapping area. The display device further includes an auxiliary wiring layer covering the via hole and connected to the overlapping area through the via hole.

Abstract: The present disclosure provides an optoelectronic device comprising a semiconductor stack comprising a first side having a first length; a first contact layer on the semiconductor stack; and a second contact layer on the semiconductor stack opposite to the first contact layer, wherein the second contact layer is not overlapped with the first contact layer in a vertical direction; and wherein the second contact layer comprises multiple contact regions separated from each other and arranged in a two-dimensional array, wherein a first distance between the two adjacent contact regions is between 0.8% and 8% of the first length.

Abstract: An electronic power device including: a first electronic power component in which all the electrodes are arranged at a first main face of the first electronic power component; and an electric contact element in which a first main face is arranged against the first main face of the first electronic power component and which includes plural separate electrically conductive portions to which the electrodes of the first electronic power component are electrically connected. The first electronic power component and the electric contact element together form a stack such that a first lateral face of each of the portions of the electric contact element, substantially perpendicular to the first main face of the electric contact element, is arranged against at least one metallization of a support forming an electric contact of the first electronic power component.