Abstract: A method and apparatus for decoding a corrupted code word is described. Decoding is accomplished by using a decoder that has a common measure of reliability for each symbol of the corrupted code word and determining whether a useful result can be obtained from the first decoder. If a useful result can not be obtained decoding the corrupted code word is accomplished with a second decoder that uses unique values of reliability for each symbol of the corrupted code word.

Abstract: An apparatus for encoding digital data for storage on a data storage medium includes a non-deterministic randomizer code generator. The randomizer code generator may select different randomizer codes for different portions of the data to be stored. The randomizer code used to randomize a given portion of the data may be stored on the media for use in subsequent data retrieval.

Abstract: A system and method for decoding a signal comprising fixed-length data (FL-data) and variable length data (VL-data) is disclosed. In one embodiment, groups of fixed length data (FL-data) and blocks of variable length data (VL-data) are stored in a predetermined space. Each group of FL-data corresponds to a block of VL-data. The blocks of VL-data are retrieved by referencing corresponding groups of FL-data. In one embodiment, this system and method permits bidirectional recovery of data. In one embodiment, this is used in the transmission of video signals over a potentially lossy communications channel.

Abstract: A method and an apparatus to calculate the CRC-32 (Cyclic Redundancy Checking) codes of a bit stream while improving the process time and simple to implement. The CRC-32 calculation is used for FCS (Frame Check Sequence) error checking code of bit stream messages sent over a fixed size packet networks when the high speeds require reducing the processing time in the network access nodes. This CRC-32 calculation is also used for FCS checking in the network equipment receiving said packetized bit stream messages. This invention applies particularly to messages conveyed via AAL5 type cells in ATM networks. The CRC-32 per byte computation of the prior art is replaced by a simple per byte CRC-R computation followed by a one pass CRC-32 computation of the R bit stream, result of the CRC-R computation.

Abstract: A test system for testing a semiconductor device by having a number of test channels (tester pins) corresponding to the number of terminal pins of the semiconductor device to be tested includes: a tester controller for controlling various operations in the tests system including test patterns to be applied to the device under test, timings and waveforms of the test patterns; a test unit for generating the test patterns and expected value patterns with predetermined timings based on control signals from the tester controller; a pin assignment converter provided between the tester controller and the test unit for providing conversion data showing a conversion relationship between physical pin numbers of the test unit and supplemental tester pin numbers which have been replaced with defective tester pins to the test unit; a test head having drivers for supplying the test patterns from the test unit to the semiconductor device with predetermined amplitudes and comparators for detecting levels of output signals fr

Abstract: The present invention pertains to a dynamic process for generating biased pseudo-random test patterns for the functional verification of a microprocessor having a bus interface unit that is capable of direct memory access (DMA) operations between I/O devices attached to an external bus and the microprocessor's memory. The test patterns verify memory operations performed by the microprocessor and DMA operations received by the microprocessor's bus interface unit. These test patterns can then be used by a simulation mechanism to simulate the expected results of the target microprocessor running the generated sequence of transactions. The test verification system categorizes the verifiable operations into transactions. Each transaction is assigned a user-defined weight that is used to bias the frequency that a transaction is tested.

Abstract: An apparatus for controlling addresses of symbol data obtained by demodulating a bit stream read from a disk for an error correction is provided.

Abstract: A rate-l/n or rate-k/n convolutional encoding method, in a digital communications system having a non-systematic convolutional encoder, includes the steps of: obtaining first to n-th block code words by multiplying first to n convolutional code generating polynomials by an information polynomial upon input of an information word; converting one of the first to n-th block code words to a systematic code word and obtaining a new information word corresponding to the systematic code word; and generating a convolutional code by encoding the new information code in the non-systematic convolutional encoder.

Abstract: A test method for a cache memory of a multiprocessor system. The multiprocessor system has a shared memory structure accessed via a system bus, including a multiplicity of processor modules, each acting as a master of the bus and each having a cache module, and a shared memory module for storing data shared by the processor modules. The test method includes dividing the cache memory into a test region, to be tested, and a code region, to store a program, positioning a test program in the shared memory at a place corresponding to the code region of the cache memory, and reading the test program stored in the shared memory and writing the test program in the code region of the cache memory to perform the test program. Accordingly, the total cache region is divided into a test region and a code region, and then only the test region is tested, to thereby enhance the test performance.

Abstract: In a semiconductor memory device including a normal memory constituted by a plurality of normal memory cells and a redundant memory constituted by a plurality of redundant memory cells, a predecoder decodes an address signal and outputs a corresponding address selection signal to an array interconnection. A normal address decoder selects a normal memory cell in the normal memory on the basis of an address selection signal from the predecoder. A redundant address decoder selects a redundant memory cell in the redundant memory on the basis of an address selection signal from the predecoder. When a defective normal memory cell in the normal memory is designated by the address signal, a control unit outputs, to the predecoder, an inactivating signal for inactivating the normal memory and a redundant memory cell selection signal for selecting the redundant memory cell in the redundant memory in place of the defective normal memory cell in the normal memory.

Abstract: A method for repeating data transmitted incorrectly (ARQ) between subscribers having in each case at least one transmit section, and at least one receive section. A data stream at the transmitting subscriber's end is subdivided into data words having a predetermined length. The data stream is combined to form data words where the individual data words are temporarily stored in a transmit buffer. The individual data words are transmitted, if necessary via a transmit unit, and are received by the receiving subscriber, if necessary in a receive unit. After temporary storage in a receive buffer the received data word is output.

Abstract: An object of the present invention is to improve the transmission efficiency and reduce circuit size in error compensating techniques where bit errors occurring during transmission are compensated for by retransmission.Transmission equipment get sequence number(s) from control information and sequence numbers which follows from the sequence number which correspond to newest data packet amongst the sequence numbers, and transmits data packet corresponding to these sequence numbers at a predetermined timing. On the other hand, reception equipment receives data packet from the transmission equipment, and manages the sequence numbers of not yet received data packets. The reception equipment then sends back sequence number(s) of predetermined number, which is smaller number than the maximum number of data packets which is sent from transmission equipment at a predetermined timing, which correspond to not yet received data packet as control information for each predetermined timing.

Abstract: A circuit board test apparatus comprising a plurality of circuit board test points is provided with an electronic analyzer comprising a plurality of test connections, each circuit board test point of the board under test being in contact with a test connection via an electrical connection. At least two of the electrical connections are electrically connected so that at least two circuit board test points of the board under test are in connection with a sole test connection.

Abstract: A self-testing smart memory (28) is provided in which memory test circuitry (46) within the smart memory (28) writes a pattern to a data RAM (32) and a broadcast RAM (34) and then reads the data RAM (32) and the broadcast RAM (34) to determine if any failures exist within the memory locations. Furthermore, a data path tester (50) determines the functionality of a data path (30) within smart memory (28).

Abstract: Sample chips are tested after determining the chip layout on a semiconductor wafer so that one or plural ones of untested chips are surrounded by plural ones of the sample chips that adjoin the untested samples. A good/defective judgment on the untested chips is performed by using predicted good/defective judgment results that are statistically predicted based on results of the sample test and stored statistical data of a defect generation profile including address information that indicates defective chip locations. As a result, the good/defective judgment can be performed with high accuracy even in a case where defective chips are localized in a particular region on the wafer in a concentrated manner.

Abstract: An on-chip processor is used as a controller for burn-in and endurance testing of embedded non-volatile memory. An automated test machine downloads a test program into the non-volatile memory. The downloaded program contains a test program to be run on the non-volatile memory. When the burn-in or endurance test equipment activates the processor, the processor executes the program and performs a test on the non-volatile memory. The same method can be utilized to perform either the burn-in or endurance tests. Only the clock and reset lines are required to operate the test. Since the clock and reset lines are part of the processor's standard inputs, the method performs burn-in and endurance testing of an embedded non-volatile memory without bringing out the memory's address, data and control lines to the package pins of the integrated circuit.

Abstract: The invention comprises an enhancement to max-log-APP processing that significantly reduces performance degradation associated with introducing the "max" approximation into log-APP computations, while still maintaining lower computational complexity associated with max-log-APP processing. This enhancement is achieved by adjusting extrinsic information produced by a max-log-APP process where the magnitude of the extrinsic information is reduced, for example, by multiplying it with a scale factor between 0 and 1.

Abstract: Main tester unit tests an IC device for presence of a defect for each of a plurality of addresses of the IC device under predetermined test conditions and stores test results for the individual addresses into a first memory. Curing analysis processing section cures each of the addresses of the IC device determined as defective, on the basis of the test results for the individual addresses stored in the first memory. To this end, the curing analysis processing section may rearrange an address logic of the IC device to replace a physical space of the defective addresses with an extra or redundant address space and thereby place each of the defective addresses in a usable condition.

Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.

Abstract: An electronic device, with a plurality of logic stages for functional collaboration, is provided with selection means for selectively operating the plurality of stages to form either a sequential logic circuit or a combinatorial logic circuit. This enables conversion of sequential logic circuitry into combinatorial logic circuitry for the purpose of effective I.sub.DDQ -testing.