Abstract: A bus control logic circuit is provided that may be tested for a variety of bus fault conditions including no-connection faults, cross-connection faults and bus-contention stuck faults. The bus control logic circuit operates in a normal mode and in a test mode. In the normal mode, the bus control logic circuit operates as a conventional driver decoder and is testable for no-connection faults and cross-connection faults. In the test mode, the bus control logic circuit also is testable for bus-contention stuck faults. To test for bus-contention stuck faults, drivers having addresses of a first parity are hard disabled and one of the hard disabled drivers is addressed. Because the addressed driver is hard disabled, the only driver that can be enabled is a non-addressed driver erroneously enabled due to a bus-contention stuck fault. To detect the bus-contention stuck fault, the signal line is placed in a known logic state that only changes if a driver is erroneously enabled due to a bus-contention stuck fault.

Abstract: A video error/distortion checker generates a difference signal from an input repetitive digital signal and a reference data signal corresponding to the input repetitive digital signal. The difference signal is compared with maximum and minimum threshold values to generate an error signal when the difference signal exceeds either threshold value. The difference signal also is used to generate a running range value that is compared with a total range value to produce the error signal when during one iteration of the repetitive digital signal the difference signal exceeds a specified range defined by the total range value. The error signal is suitably displayed, either visually or alphanumerically or both, so that an operator may recognize the type, severity and location of errors in the repetitive digital signal.

Abstract: The present invention is directed to a system comprised of a computer, at least one integrated circuit tester, a communications link enabling communications between the integrated circuit tester and the computer, and a computer-readable medium. The computer-readable medium contains a sequence of instructions that, when executed, create a set of tests for integrated circuit testing. The set of tests may include only those tests that are calculated to be statistically significant. A second set of tests may be created that includes only those tests that are calculated to be statistically insignificant. The computer monitors the test results and moves tests between the two sets to ensure that only statistically significant tests are in the first group and that only statistically insignificant tests are in the second group.

Abstract: In an error-correcting decoder, in which an input digital signal including reliability information is decoded by using a Viterbi algorithm as a first decoding process and a final decoded result is obtained by block-code decoding as a second decoding process, a flag signal is added to a location where a value of reliability of path metric determined by the Viterbi algorithm is lower than a threshold, as an original flagged location. A flag signal adding unit continuously adds flag signals to locations, from the original flagged location to locations preceding the originally flagged location, after back tracing. The flagged locations are then regarded as erasure locations in the block-code decoding process.

Abstract: For a transmission system in which (a) a received sequence of symbols is processed by an inner decoder followed by an outer decoder and (b) the inner decoder is capable of providing to the outer decoder more than one output sequence corresponding to the received sequence, the decoded sequence released by the outer decoder is screened for errors undetected by the outer decoder, if a predetermined criterion is satisfied.

Abstract: A method and data structure for a header-formatted defective sector management system. A spare sector is allocated for each n sectors. When a defective one of the n sectors is identified, the sectors are slipped using the spare sector. The location of the defective sector and the type of defect, e.g., data field or header field, is indicated by a data structure written to the header field of at least one of the non-defective sectors. When a second defective sector is identified, the system operates to disposition the second defective sector based on the type of the first defective sector. If the first defective sector was a defect in the data field and the second defective sector is a defect in the header field then the first defective sector is converted to a reassigned sector and the second defective sector is slipped. This avoids the problem of reassigning a sector having a defective header field.

Abstract: In a DRAM, a boosted voltage Vpp is applied to a selected word line WL1 in a normal mode. In a test mode, a power supply voltage Vcc at a level lower than Vpp level is applied onto selected word line WL1. High data written into memory cell in the test mode of the DRAM is at the level lower than that of the high data written into memory cell in the normal mode. Therefore, a time before an H.fwdarw.L error occurs can be reduced, and a test time can be reduced.

Abstract: There is disclosed an integrated circuit comprising a test access port controller having a first mode of operation in which it is connectable to test logic to effect communication of serial test data and the control of an incoming clock signal, and a second mode of operation in which a data adaptor is connected to input and output pins via the test access port controller, the data adaptor being supplied with parallel data and control signals from on-chip functional circuitry and converting such parallel data and control signals into a sequence of serial bits including flow control bits.

Abstract: Error correction code (ECC) encoding is performed by using a first ECC encoding means to add a first check code to each of a number of first code groups included in a code sequence. Additionally, a second ECC encoding means is employed to add a second check code to each of a number of second code groups. The second check code is extracted from a predetermined number of successive first code groups in the code sequence.

Abstract: An error correction apparatus corrects erroneous data and reduces deformation of a displayed picture when inputted data are high frequency data around the erroneous data. R, G and B channel signals of data are inputted via input nodes 1a, 1b and 1c. A controller generates signals ch1 and ch2 which specify the erroneous data channel and a channel for data correction according to a control signal C from an error detection circuit. A correction data circuit generates correction data. For example, if G(i) is assumed to be erroneous data, the correction data circuit generates correction data as G'(i)=R(i)+G(i+1)-R(i-1) based on the previous data G(i-1) provided by a delay circuit and the data of the other errorless channel. The erroneous data G(i) is replaced with the correction data G'(i) and a set of corrected data R(i), G'(i) and B(i) is outputted as output data.

Abstract: Testing of a multi-module data processing system (20) includes performing a functional test on a module (42, 44, 46, 48, 50, 54) concurrently with an erase operation of a non-volatile memory module (34, 36). Because the erase operation requires multiple clock cycles to complete, and little or no interaction with a tester, a set of test patterns may be run on one or more of the modules (42, 44, 46, 48, 50, 54) while the erase operation is being performed. Between each test pattern, a special reset signal is provided to a reset unit (39) of a system integration unit (38). The special reset signal resets the modules (42, 44, 46, 48, 50, 54), without affecting the erase operation of the flash memory module (34, 36), in order to perform each test of the modules (42, 44, 46, 48, 50, 54) from a known state. Concurrent testing in this manner reduces the time required to test a multi-module data processing system.

Abstract: Automatic test equipment for semiconductor devices. The automatic test equipment contains numerous channels of electronic circuitry in which precisely timed test signals are generated. Significant advantages in both cost and size are achieved by incorporating multiple channels on one integrated circuit chip. To allow this level of integration without degrading timing accuracy, a series of design techniques are employed. These techniques include the use of guard rings and guard layers, placement of circuit elements in relation to the guard rings and guard layers, separate signal traces for power and ground for each channel, and circuit designs that allow the voltage across a filter capacitor to define a correction signal. Another feature of the disclosed embodiment is a fine delay element design that can be controlled for delay variations and incorporates calibration features. A further disclosed feature is circuitry that allows the tester to have a short refire recovery time.

Abstract: Test data TD, which are provided to a flipflop 11 of a scan flipflop 10-1 through a scan path 1S are latched with the timing of a clock signal CK that has been inverted at an inverter 12. An output signal S11 from the flipflop 11 is provided to a flipflop 14 via a selector 13, is latched at the flipflop 14 with the timing of the clock signal CK and is provided to a scan flipflop 10-2at the succeeding stage through a scan path 3S. In this manner, since the timing with which the test data TD change and the timing with which the clock signal CK rises are offset by 1/2 of the clock cycle, a reliable scanning operation is achieved regardless of the length of the paths such as the scan path 1S and the like.

Abstract: A method a system for automatically controlling an adaptive interleaver involves monitoring performance parameters of a transmission system and controlling the adaptive interleaver in response to the performance parameters. The SNR and the data rate of the transmission system are preferably determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the SNR. Alternatively, the BER and the data rate of the transmission system are determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the BER. Alternatively, any one of the SNR, BER or data rate can alone be monitored and used to the adaptive interleaver. The system provides a effective system for adjusting an adaptive interleaver in response to performance parameters of a transmission system.

Abstract: A diagnostic method (100) with pre-assembly fault recording lock-out inhibits fault recording during assembly of a main system until the system has been determined operation at least once (116). The method will still note the detection of system failures/errors (112) by activating a warning lamp (120), but will not record these faults into memory until the system has determined that the main system has been powered up without any errors at least once (118 and 122). Thus, since these faults are not stored in memory during manufacture/assembly, the method of the present invention obviates the need for any additional assembly step(s) of erasing and/or clearing the memory, or externally controlled recording inputs for the diagnostic system.

Abstract: Bit stream data that contains a digital video signal and character data is input to a decoding apparatus. Bit map character data is extracted by a demultiplexer 1 and supplied to a data decoder 7. A word detecting portion 20 of the data decoder 7 detects a line that has error data. A line processor 40 detects a line that has error data and stores an address of the end of the line to a register. Thus, when data is displayed, while it is being read from a buffer memory 22 and decoded, the buffer memory is randomly accessed. Consequently, a particular line can be displayed a plurality of times. Alternatively, a particular line can be skipped. Instead of reading data of a line that has an error, by accessing lines that immediately precede or immediately follow the line that has the error in the memory, character data can be interpolated for each line.

Abstract: A low-overhead scheme for built-in self-test of digital designs incorporating scan allows for complete (100%) fault coverage without modifying the function logic and without degrading system performance (beyond using scan). By altering a pseudo-random bit sequence with bit-fixing logic at an LFSR's serial output, deterministic test cubes that detect random pattern-resistant faults are generated. A procedure for synthesizing the bit-fixing logic allows for complete fault coverage with low hardware overhead. Also, the present approach permits the use of small LFSR's for generating the pseudo-random bit sequence. The faults that are not detected because of linear dependencies in the LFSR can be detected by generating more deterministic cubes at the expense of additional bit-fixing logic.

Abstract: A method and apparatus for testing a semiconductor chip includes providing the semiconductor chip with a common input/output (I/O) or bidirectional I/O pad. The I/O pad is electrically coupled to an off-chip driver (OCD) and an off-chip receiver (OCR). The OCD, I/O pad, and OCR are combined in a common input/output (CIO) or bidirectional I/O configuration. The I/O pad is effectively open circuited by an external tester and a performance parameter of the IO circuits connected to the open circuited pad is tested.

Abstract: A scheme for accessing a control register bus and control registers of a microprocessor through a test access port which is configured to an established testing standard. A test access port (TAP) of a microprocessor is configured to communicate serially based on a technique specified in the IEEE 1149.1 standard. External serial instructions are converted for parallel transfer to provide control signals for accessing the internal structures. Serial address and data signals are also converted for parallel transfer to access internal structures on a control register bus and parallel outputs are converted to serial format for external output. By permitting external access to low level internal bus architecture, system testing and debug can be performed by utilizing external programming.

Abstract: A method for generating test patterns for testing digital electronic circuits, whereby a test pattern template is defined that fully specifies some primary inputs while other primary inputs are specified in accordance with selected series of codes. The test pattern template is then repeatedly converted into a stimulus pattern using different integers in the selected series of codes, and fault simulation is performed on a circuit under test using each stimulus pattern. A stimulus pattern is then saved for subsequent testing of the circuit under test whenever fault simulation using that stimulus pattern shows that fault coverage has increased. The method significantly reduces the number of primary input combinations required for generating test patterns.