Abstract: A dual speed hub includes a CPU, two hubs of different transmission speeds, two MACs (media access controls), and a switch, wherein the CPU periodically sends a test packet in proper order through one MAC, one hub, the switch and the other hub to the other MAC, then checks the receiving condition and the content of the returned test packet, then determines the normality of the function of the switch subject to the receiving condition and the content of the returned test packet, and then provides a warning signal to a network management system when the switch is judged abnormal, informing the network manager to repair the switch.

Abstract: A tester circuit generating differential signals, single ended signals, or a fast transitioning signal to exercise inputs of a device under test is described. According to one embodiment, the tester circuit includes a first circuit configured to generate a first test signal on an input of the first driver. The tester circuit also includes a second circuit configured to generate a second test signal on an input of a second driver. Further, the tester circuit also includes select signals and select logic to determine the different testing modes of the device under test.

Abstract: Concurrent Fault Detector Circuits (CFDCs) are test components of a main system, e.g. an Application Specific Integrated Circuit, and provide the results of the tests in parallel to at least one Error Source Register (ESR). Instead of reading out the ESR in parallel, its contents are copied to a serial shadow register so the contents can be read out in series to an error correcting application, thus reducing the number of output pins and the burden on resources of the main system. The ESR's receipt and transfer of information is under the control of a Boundary Scan Interface. In one embodiment, the test results are prioritized and compared to data in a mask register so that only important errors create a system interrupt which causes the read out of data from the shadow register.

Abstract: A circuit arrangement utilizes a common bus for functional operations of logic circuits and for scan testing the logic circuits. In one embodiment, input/output ports and scan test ports of the logic circuits are switchably coupled to a bus. For functionally testing the logic circuits, a predetermined command transmitted over the bus causes the scan test ports to be coupled to the bus and the input/output ports to be decoupled from the bus. Test data may then be transmitted to and from the logic circuits via the bus. When testing is complete, a second predetermined command transmitted over the bus causes the scan test ports to be decoupled from the bus and the input/output ports to be coupled to the bus.

Abstract: Data or its inverse, is written into a regular structure, such as a RAM, while stepping through the address range. The data is then read out and a determination is made as to success or failure. The scheme is based upon a Johnson counter being the source of the data, or its inverse. This style of counting has the unique property that, every time a "count" takes place, the parity associated with the Johnson counter output will "toggle," since only one bit is allowed to change. Reliance on this parity toggling determines possible failures.

Abstract: A semiconductor integrated circuit (1) has a scan test circuit (6) and a target test circuit (4), connected to a CPU (3) and a RAM (2) through internal buses (5a and 5b) that are mounted on a same semiconductor chip. The scan test circuit (6) provides test signals to the target test circuit (4) having a plurality of flip flops connected one another in a line like a string of beads as a shift register.

Abstract: An event driven system for testing logical operations of logic elements of an integrated circuit including an oscillation element. The system uses in/out data of the logic elements and net-list data of the logic circuit. An incoming event of the oscillator element has a signal incoming time and a signal incoming place, indicating a change in a signal by oscillation of the oscillation element. An incoming process of the incoming event includes generating a normal event having the same incoming time and the same incoming place as the incoming event, and generating a new incoming event having the same incoming time as the incoming event, but a different incoming time. The different incoming time is a changing time of a signal caused by oscillation of the oscillator element. The changing time is later than the incoming time of the incoming event.

Abstract: An apparatus for producing test data used for detection of defects which occur in manufacturing functional blocks of a processor LSI is provided with a test pattern producing part for detecting a fault of the functional block at a block edge of the functional block, based on logic data of the functional block, with regard to one operation of the processor LSI which operates the functional block for the test data to be produced, the test pattern at the block edge of the functional block being such as to satisfy the conditions of an input signal to the block edge of the functional block when an instruction on the one operation is executed, and the conditions of an output signal from the block edge of the functional block being observable from the outside of the processor LSI when the instruction is executed.

Abstract: A parity check circuit for inspecting a piece of binary information having n bits including a parity bit provided with n EXCLUSIVE-OR circuits for receiving each bit of the piece of binary information, at least one stage composed of EXCLUSIVE-OR circuits having the number of a half of the previous stage until the number of the EXCLUSIVE-OR circuits reaches one, and an error detector, further including at least one data register circuit intervening between each of the stages and for receiving a set of data from the previous stage, forwarding the previous set of data which has been registered therein toward the next stage, and registering the set of data newly delivered to the stage, in response to a check signal.

Abstract: A pattern generator to be used in a semiconductor test system for testing a semiconductor device having function modules common to other semiconductor devices and specific function modules unique to the semiconductor device under test includes, a first pattern generation block for generating test patterns for testing the common function modules in the semiconductor device under test, a second pattern generation block for generating test patters for testing said specific function modules in the semiconductor device under test, and a pattern combine circuit which is connected to the outputs of the first and second pattern generation blocks and transmits the test patterns from either one of the first or second pattern generation block, wherein the first pattern generation block sends a start signal to the second pattern generation block to initiate the operation of generating the module specific test patterns, and the second pattern generation block sends an end signal to the first pattern generation block to in

Abstract: A system comprising devices connected via a 1394 serial bus solves a problem that if omission of data packet occurs in isochronous transfer capable of high-speed data transfer, only data without the omitted data packet is sent to a transfer destination. A recording/reproduction device 101 repeatedly sends image data stored in a storage medium by the isochronous transfer, and a printer 102 receives the image data repeatedly sent by the isochronous transfer. If a data packet has been omitted in the received data, the omitted data packet is obtained from the data repeatedly sent by the isochronous transfer, thus the printer 102 can print an image based on the complete image data.

Abstract: A method to identify and test primitive faults in combinational circuits described as multi-level or two-level netlists. A primitive fault is a multiple path delay for which none of the single paths contained in the fault is robustly or non-robustly testable while the presence of the fault will degrade the circuit performance. Identification and testing of primitive faults is important for at least two reasons: (1) a large percentage of paths in production circuits remain untestable under the single-path delay fault model, (2) distributed manufacturing defects usually adversely affect more than one path and these defects can be detected only by analyzing multiple affected paths. The single-path delay faults contained in a primitive fault have to merge at some gate(s). The methodology for identifying primitive faults can quickly (1) rule out a large number of gates as possible merging points for primitive faults, and (2) reduce or prune the combination of paths that can never belong to any primitive fault.

Abstract: An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.

Abstract: A quick retry operation is possible by outputting an error flag pertaining to a sector after error correction processing of digital data. When an output of an error detection flag unit for a correction block indicates the existence of an uncorrectable error, the sectors are checked to see if the sectors corresponding to retrieved data include any error or not based on output from a sector error flag register B. When the sectors are judged as error, signals are retrieved again from a storage medium, restored in a memory, and an error correction processing is repeated again. The data such as that of P pictures or B pictures of MPEG which can be reproduced even with errors are output even when the error detection flag unit indicates the existence of the uncorrectable error. It enables identification of the sectors with the errors and simplifies the following operations pertaining to the error at a data receiving side by outputting the error flag along with the data.

Abstract: To monitor the correct function of a microprocessor, microcontroller or any other program-controlled circuit data processing results are checked in the working cycle for correlation with data which are produced independently of the circuit to be monitored and independently of the program run in a monitoring circuit. If deviations indicative of a malfunction occur, a disabling signal is generated. To this effect, data words or a data word sequence is produced in the program run of the circuit to be monitored and transmitted to the monitoring circuit at predetermined times. The content of the data words and the timely appearance of the data words is monitored by way of the monitoring circuit. (FIG.

Abstract: A deinterleaver includes a first storage unit for storing data an order of which is rearranged from a correct order to a random order, a data latching unit for temporarily holding output data of the first storage unit, a second storage unit for storing output data of the data latching unit, and an addressing unit for generating a read addressing signal which is outputted to the first storage unit, and a write addressing signal which id outputted to the second storage unit. The addressing unit includes a counting unit for counting a clock to generate the read addressing signal, and an arithmetic unit for generating the write addressing signal for rearranging to the correct order using the read addressing signal outputted from the counting unit.

Abstract: A plurality of generator polynomials are prepared for error correction and stored in a table by assigning a specific table number to each generator polynomial. Each generator polynomial provides a different error correction capability so that a different number of error correction bits are added to each set of transmission data. For radio communication, an electric field intensity is first measured, and in accordance with this electric field intensity, a generator polynomial to be used at that time for error correction calculation is determined. It is therefore possible to change the number of error correction bits in accordance with the environment at that time and to perform efficient error correction. For example, if a base station is in a near area, an error rate is small so that the number of addition bits is reduced.

Abstract: A semiconductor device testing apparatus for a memory- built-in logic LSI or the like, which has a hardware configuration that test patterns for logic and memory sections of the semiconductor device can be described independently of each other.

Abstract: A method of testing high speed interconnectivity of circuit boards having components operable at a high speed system clock, employing an IEEE 1149.1 standard test method in which test data is shifted into and from the components at the rate of a test clock during Shift.sub.-- In and Shift.sub.-- Out operations, and having an Update operation and a Capture operation between the Shift.sub.-- In and Shift.sub.-- Out operations, the components including a first group of components capable of performing the Update and Capture operations at the rate of the Test Clock only and a second group of components capable of performing the Update and Capture operations at the rate of the system clock, the method comprising the steps of performing the Shift.sub.

Abstract: A physical packaging position processing system of an exchange having exchange proper software and a terminal unit connected to the exchange and having terminal software. The exchange proper software has a system fixed database which is common to the whole of the system and which stores, in a hierarchical structure, a name table of frame unit name, frame name and module name and a name table of module main body name and card name carried in the module. Upon the system construction, a maintenance man prepares a physical packaging position database by utilizing the information of the system fixed database.