Abstract: An integrated circuit memory is described which has a multi-bit write register. Each plane of the multi-bit write register has a plurality of bits, or columns. The multi-bit write register allows each memory cell in a block of selected memory cells of the integrated circuit memory to be block written to a different logic state. The write register can be a color register in a multi-port memory device, or a single port device. Several methods of loading the write register are also described. These methods include loading the write register one column at a time or one plane at a time. The columns or planes can be loaded in either a pre-determined pattern, or selectively loaded.

Abstract: A non-volatile, integrated circuit memory, such as a Flash EPROM, including an array 1 of memory cells 10, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. Included is a decoder circuit 16 having a plurality of input lines 94, 96, for each row in the array, and having as outputs the row lines 15. The decoder circuit includes a decoder logic circuit associated with each row line, the decoder logic circuit including a plurality of low power logic devices 84-90 interconnected to perform a predetermined decoding function on the signals on the input lines for the associated row line to apply a signal to an associated row node when the decoder logic circuit determines that the associated row line is selected.

Abstract: A semiconductor memory device is disclosed that provides replacement of defective main memory portions with operational redundant memory portions. The device includes fuse circuitry that comprises both nonvolatile and volatile memory portions. Because the fuse circuitry includes a volatile memory portion in addition to a nonvolatile memory portion, additional functionality may be achieved by the fuse circuitry. For example, the volatile portion of the fuse circuitry allows the retention of the nonvolatile portion of the circuitry to be tested using standard testing techniques. In addition, the volatile memory portion provides a way for easily utilizing unused redundant memory. In one embodiment of the present invention, a semiconductor memory device is provided that uses nvSRAM cells as the main storage element in the main memory area, the redundant memory area, and in the fuse circuitry.

Abstract: A memory device module in a package having externally accessible contacts includes multiple integrated memory circuits accessible to external circuitry exclusively through the contacts. An accessing circuit for each memory circuit accesses memory cells in the memory circuit for communication with the external circuitry. Each accessing circuit can be enabled to access redundant memory cells instead of inoperative memory cells by an enabling signal. An enabling circuit for each accessing circuit can output the enabling signal in response to receiving a unique set of input signals from external circuitry. Each unique set is selected with fuses in each enabling circuit, and includes row and column address strobe signals and a data signal. Upon receiving its unique set, one of the enabling circuits advantageously enables its associated accessing circuit to access redundant memory cells without the accessing circuits of the other memory circuits also being so enabled.

Abstract: The present invention is related to an interface circuit for transmitting data corresponding to a specific address from/to a decoding memory unit, includes a bit-selection circuit pre-set therein a transmission mode, and a processing circuit electrically connected to the bit-selection circuit for transmitting the data according to the transmission mode. The present invention also relates to methods for reading out and writing in data corresponding to a specific address from/to a decoding memory unit.

Abstract: A semiconductor memory including first, second, and third data busses, and first and second memory cell arrays arranged among the first, second, and third data busses. During operation of the semiconductor memory, a first, a second, and a third circuit selectively couple the first, second, and third data busses to a fourth and a fifth data bus. Additionally, there is provided first and second buffer circuits, which are respectively coupled to the fourth and the fifth data busses, and a sixth data bus, which is commonly coupled to the first and second buffer circuits. A control circuit is used to control the operation of the switch circuits. In preferred embodiments, the number of buffer circuits in the semiconductor memory is less than or equal to the number of memory cell arrays.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacitor. The capacitor is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using a structure with decreased resistance such as silicided structure. In addition, there are made common the processing for lowering the resistance of the gate electrode of the transfer MISFETs and the processing for forming the local wiring lines.

Abstract: A circuit and method for testing on-chip memory for a microprocessor or a microcomputer is disclosed. The memory test circuit includes an input register, an output register, an adder, and a sequencer to control the test process. The process includes receiving a simple communication protocol from the control unit to start the test, running a common memory test such as a checker board, AAAAh, 5555h and the like, and then storing the test results in an output register. The test circuit can include a bi-directional RESET signal means for disabling the system while the microprocessor or microcomputer runs its memory test.

Abstract: A driver circuit writes data to a memory cell during a write cycle and uncouples the write power terminals from the write terminals during a test mode. The driver circuit includes a first and second data input terminals that typically receive complementary data signals during a write cycle, a test terminal, a write-enable terminal, first and second write power terminals, and first and second write terminals that are coupled to the memory cell. The circuit respectively uncouples the first and second write terminals from the first and second write power terminals when a first signal level, which indicates the test mode, is present on the test terminal. The driver circuit may also couple the first and second write terminals to a reference voltage such as a ground voltage when the first signal level is present on the test terminal.

Abstract: A semiconductor memory including first, second, and third data busses, and first and second memory cell arrays arranged among the first, second, and third data busses. During operation of the semiconductor memory, a first, a second, and a third switch circuit selectively couple the first, second, and third data busses to a fourth and a fifth data bus. Additionally, there is provided first and second buffer circuits, which are respectively coupled to the fourth and the fifth data busses, and a sixth data bus, which is commonly coupled to the first and second buffer circuits. A control circuit is used to control the operation of the switch circuits. In a preferred embodiment, the semiconductor memory has an equal number of buffer circuits and memory cell arrays.

Abstract: A method for programming an array of memory cells, wherein each memory cell has at least three possible states. The method comprises the steps of 1) analyzing a set of data to be programmed into the array of memory cells to determine destination states for each of the memory cells in the array, and 2) programming all memory cells to be programmed to a particular destination state, up to a maximum number of memory cells being programmed at any given time, until all memory cells having a particular destination state are programmed, whereupon all memory cells to be programmed to a next destination state are programmed in a like manner.

Abstract: Circuitry and methods for performing a global erase of an array of electrically-erasable programmable read-only memory (EEPROM) transistors are provided. The voltages used to erase the EEPROM transistors are controlled so that the maximum voltage across the gate oxide of previously erased transistors in the array does not exceed a predetermined maximum acceptable voltage level, thereby avoiding gate oxide damage due to high electric fields.

Abstract: A memory circuit is described which increases the density of memory cells by including a reference circuit. The memory circuit has an open digit line architecture where sense amplifiers use two digit lines to sense data stored in the memory cells. One of the digit lines is used as a reference while the other digit line is active. A reference circuit is described which can be used to replace one of the digit lines connected to the sense amplifier circuit. The reference circuit models the electrical characteristics of a digit line by including a capacitor and a transistor, each sized to match the characteristics of a digit line.

Abstract: A memory cell array of a dynamic semiconductor memory device is divided into a plurality of memory cell blocks. A block selecting circuit selects and refreshes larger number of memory cell blocks in refreshing mode than the number of those selected during normal mode. Sense amplifiers in the memory cell blocks selected by the block selecting circuit are selectively driven with smaller driving force in refreshing mode than that in normal mode. More preferably the driving force is changed during the amplifying operation so as to achieve both the high sensitivity and the suppression of the peak value of the operational current.

Abstract: In a semiconductor memory device including a memory cell array, a sense amplifier for sensing a voltage of a selected one of read-only memory cells of the memory cell array, a dummy memory cell array, a reference voltage generating circuit for sensing a voltage at the output of the dummy memory cell array, and a comparator for comparing a sense voltage of the sense amplifier with a reference voltage of the reference voltage generating circuit, a bias circuit supplies a bias current from a power supply terminal to the output of the sense amplifier and also supplies a bias current from the power supply terminal to the output of the reference voltage generating circuit.

Abstract: A DRAM includes a refresh controller including a clock control section for producing a refresh mode signal in response to an external control clock signal, a refresh logic section for producing an enable signal in response to the refresh mode signal, a refresh counter for sequentially producing a first plurality of row address signals during an active period of a row address strobe signal in response to the enable signal, a row address buffer for producing a second plurality of row address signals in response to the row address signals, and a row decoder including a plurality of word line drivers which sequentially decode the second plurality of row address signals provided from the row address buffer and sequentially enables word lines corresponding to the decoded row address signals.

Abstract: A memory device includes an array of memory cells arranged in rows and columns. A row-address decoder allows a row address to propagate therethrough while a row address strobe is at an inactive logic level. In response to a transition of the row address strobe from the inactive level to an active level, the decoder enables a row of memory cells selected by the row address. A row-address latch stores the row address in response to the transition of the row address strobe. The memory device may also include a transition detector that monitors the row address for a transition thereof. A delay circuit is coupled to the decoder, the latch, and the detector. If the monitor detects a transition of the row address, the delay circuit delays the enabling of the row of memory cells and the storing of the row address at least predetermined time after such a transition.

Abstract: A circuit and method for testing on-chip memory for a microprocessor or a microcomputer is disclosed. The memory test circuit includes an input register, an output register, an adder, and a sequencer to control the test process. The process includes receiving a simple communication protocol from the control unit to start the test, running a common memory test such as a checker board, AAAAh, 5555h and the like, and then storing the test results in an output register. The test circuit can include a bi-directional RESET signal means for disabling the system while the microprocessor or microcomputer runs its memory test.

Abstract: An object of the invention is to vary data width by changing over the readout mode, to change over the number of operating sense amplifiers in order to minimize the readout current, and to reduce the power consumption. A switch circuit operates only half of sense amplifiers by a first EN1 signal when the output data width is set at 8 bits by data width control signal BYTE. At this time, other sense amplifiers are not put in action, and hence the power consumption is saved. When the external output is 16 bits, all sense amplifiers are put in operation. Besides, in the case of internal readout operation such as verification by internal state signal RUN, all sense amplifiers are operated to perform an efficient high speed operation.

Abstract: Power output switching circuit (215) for use in high current and high frequency applications. The output circuit provides a series of geometrically symmetric parallel spaced semiconductor converters (214A, 214B, 216A, 216B) arranged such that the voltage for each semiconductor output device is substantially equal and minimal for each device. In this way, each device exhibits substantially the same impedance, such that circuit performance is largely a function of intrinsic device characteristics, and substantially independent of cross coupling and another external influences.