Abstract: Integrated circuit chips with multiplexed input/output pads include means for expanding the functional and diagnostic capability of the circuit by increasing the effective number of input/output pads connected thereto so that more information can be provided to and from the chip. In particular, multiplexing means preferably provides the capability of accessing any one of a plurality of signal lines in the circuit from each input/output pad. This expanded capability is preferably achieved using one or more selection control signals which can be generated internally or externally to a chip containing the integrated circuit.

Abstract: A semiconductor memory device having a shortened test time and a column selection transistor control method therefor.

Abstract: A method and apparatus for reducing noise in a memory bit-line pull-up circuit. The memory bit-line pull-up circuit includes a first reference line, a second reference line, a first capacitor, a gating device, and a pull-down circuit. The circuit may further include a load transistor coupled between the first reference line and a first voltage conduit, which generally maintains the voltage on the first reference line at Vcc-Vt, and a second capacitor and the load transistor providing a pull-up path for the voltage on the first reference line when Vcc increases and the first capacitor. The pull-down circuit provides a pull-down path for the voltage on the first reference line when Vcc decreases. The first capacitor provides a pull-up path for the voltage on the second reference line. A first gating device couples a bit-line to the first reference line. The circuit further including a second gating device to couple a bit-line bar to the first reference line.

Abstract: In an idea processor, a plurality of sentences are managed in a hierarchical structure having a plurality of levels. Eight or less sentences are developed from a key sentence, and these nine or less sentences are displayed in a nested structure on a screen such that the key sentence is displayed at the center cell of nine cells arranged in a 3.times.3 matrix, while the developed sentences are displayed in cells that surround the center cell. Since the number of sentences that are developed from the key sentence is limited to eight, the idea processor is easier for a beginner to use, as compared to a conventional idea processor in which the number of sentences that are developed from a key sentence is not limited. Moreover, the nested displayed 3.times.3 cell structure makes it easier to grasp the entire structure of the sentences on a screen.

Abstract: A word line voltage boosting circuit varies a word line output voltage according to variation of the number of the word lines to be activated. A boosting circuit boosts a word line voltage which has been precharged to a first level voltage to a second level voltage in response to an activation signal. A voltage adding circuit further boosts the word line voltage to a third voltage level by adding a predetermined voltage to the second level voltage if the number of the word lines to be activated increases. A driving circuit includes a bootstrap circuit for stably providing the boosted word line voltage to an output line.

Abstract: There are provided a MIS transistor having a substrate portion, a gate, a source, and a drain, a back-bias generator to be applied to the substrate portion of the MIS transistor, and a resistor interposed between the substrate portion of the MIS transistor and the back-bias generator so that the potential between the both ends thereof changes in a range from one value in the active mode to the other value in the standby mode of the MIS transistor. In the MIS transistor, the back bias is self-regulated so that it approaches to zero in the active mode, while it moves away from zero in the standby mode. Consequently, the threshold voltage is reduced in the active mode due to the back bias approaching to zero, so that higher-speed operation is performed. On the other hand, off-state leakage is suppressed in the standby mode due to the back bias moving away from zero. Thus, it becomes possible to constitute a semiconductor apparatus which operates at high speed with low power consumption.

Abstract: When a data is read out from a memory cell, a current mirror circuit is operated in response to detection of potential variation of a first data line, so that charge of a second data line is discharged by the current mirror circuit. At this point, a control transistor interposed between the first data line and the second data line is operated in a saturation region. As a result, the impedance between the first data line and the second data line becomes substantially infinity, and the two data lines are substantially open-circuited. Thus, the current mirror circuit discharges merely the second data line with a small load capacitance in a short period of time, resulting in a high speed read operation. Therefore, even when the first data line, to which a large number of memory cells are connected, has a large load capacitance, the read rate is increased.

Abstract: An improved high-speed sense amplifier is disclosed for use in programmable logic devices (PLDs) and complex PLDs. The sense amplifier includes a transresistance amplifier portion that provides a voltage potential to a first node of a memory array, which defines a read product term line. The current drawn by the memory array will cause the output of the amplifier to change states once a predetermined current level is reached, the predetermined trip point indicating that at least one memory cell is conducting. The amplifier includes an n-channel MOS transistor having its drain connected between a second node of the memory array, and its source to ground. The gate of the n-channel transistor is connected to the read product line. The n-channel limits current through the memory array by raising the potential at the second node, thus reducing the voltage drop across the memory array.

Abstract: A P-channel flash EEPROM cell has P+ source and P+ drain regions, and a channel extending therebetween, formed in an N-type well. A thin layer of tunnel oxide is provided over the channel. A poly-silicon floating gate and poly-silicon control gate, separated by a dielectric layer, overlie the tunnel oxide. Programming is accomplished via hot electron injection while erasing is realized by electron tunneling. The threshold voltage of the cell may be precisely controlled by the magnitude of voltage coupled to the floating gate during programming. Since the injection of hot electrons into the floating gate is independent of variations in the thickness of the tunnel oxide layer and the coupling ratio between the floating gate and the control gate, programming operations and data retention are not affected by process variations.

Abstract: A semiconductor circuit has a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and fourth transistors are a first conduction type, and the second and third transistors are a second conduction type opposite to the first conduction type. The semiconductor circuit employs a first power supply line for supplying a first voltage, a second power supply line for supplying a second voltage, and a third power supply line for supplying a third voltage outside of the range determined by the first voltage and the second voltage. The first, second, and third transistors are connected in series between the second power supply line and the third power supply line, and the fourth transistor is connected between an input terminal and a control electrode of the first transistor.

Abstract: A semiconductor memory device has the skew between the individual transmission lines of a parallel transmission bus minimized by the addition of respective load transmission lines to each of the individual transmission lines in the parallel bus. A first circuit unit including a first parallel bank of internal circuits for generating internal control signals is formed adjacent to a predetermined region within a chip. A second circuit unit includes a second parallel bank of internal circuits for performing a predetermined operation in response to an output of the first circuit unit. The second circuit transmits signals to the first circuit over a parallel bus comprised of a plurality of transmission lines connected respectively between the individual internal circuits of the first and second circuit units. A plurality of load transmission lines are connected respectively to predetermined portions of the individual transmission lines to thereby equalize the loads of the transmission lines.

Abstract: In a memory device such as a DRAM or multiport DRAM, each of a plurality of memory cells includes an access transistor with a gate connected to a word line and a storage capacitor with a storage node connected through the access transistor to a digit line. Data is transferred on the digit line to and from the storage capacitor when the word line is activated and the access transistor enabled thereby. According to the present invention, a timing control circuit is provided to control deactivation of the word line. The timing control circuit includes a digit-write/transfer model that simulates a read-write cycle in a DRAM or a serial write transfer operation in a multiport DRAM. The digit-write transfer model produces an output signal indicating the state of the modeled data transfer operation. The timing control circuit also includes a reference voltage circuit and a level comparator. The level comparator compares the model output signal to the reference voltage provided by the reference voltage circuit.

Abstract: A boundary independent decoder for a Synchronous Dynamic Random Access Memory (SDRAM) with an n bit burst transfer block length. A user, usually a processor or microprocessor requests access to a block of SDRAM memory. The requested block may begin between array decode boundaries. A column address is decoded by an SDRAM column decoder. The decoder selects a starting boundary for 2n bits. The first requested bit is in the first n bits of the 2n selected bits. Thus, the entire n bit block is included in the selected 2n bit block. The n bit block is selected from the selected 2n bits and latched in a high speed decoder/register in a sequentially scrambled order, i.e., the i.sup.th bit is the first requested bit and the requested bit order is i, . . . , (n-1), . . . , 0, . . . , (i-1). Latched data is scrambled either sequentially or interleaved, if required. Scrambled data is burst transferred off chip.

Abstract: A roll call circuit includes a series arrangement of a fuse and a switching element connected between a power supply terminal and a ground voltage terminal. The switching element is controlled by an internal test signal.

Abstract: Integrated circuit chips with fuse-based mode selection capability include a first signal generator for storing a first logic state when the fuse is blown, in response to an externally generated input signal, and for generating a first option changing signal based on the stored first logic state. To reduce the susceptibility to noise and inadvertent designation signals, a second signal generator for storing a second logic state when the fuse is blown is also provided and that fuse is blown in response another externally generated input signal. However, rather than blowing the fuses of the first option changing signal generator and the second option changing signal generator by applying external input signals simultaneously, the fuses are blown sequentially by connecting the second option changing signal generator in series with the first option changing signal generator so that the second option changing signal cannot be generated unless the first option changing signal generator has already been generated.

Abstract: Circuit and method are presented for activating/deactivating a special operational mode at power-on of an integrated circuit device having no industry defined test state and/or dedicated test pin. The operational mode is enabled upon powering on the integrated circuit combined with detection of a predefined pattern of a first logic state and a second logic state clocked in successive cycles within a first standard input signal, such as an output enable signal, for a normal operating mode of the device. Special non-functional processing is then performed, such as reading prestored identification data from the integrated circuit and/or testing the integrated circuit via embedded test circuitry including boundary scan or other diagnostic circuitry. This special operational mode is deactivated upon receipt at the integrated circuit device of a second standard input signal, such as a write signal for a random access memory (RAM) device, of a predefined logic state (e.g., write enable state).

Abstract: A reference circuit including a reference cell for generating a reference current in response to a control voltage. The reference current is received by a first branch of a first current mirror circuit and a matched current is generated in a second branch of the mirror circuit. An output device is connected to receive the matched current and to supply a reference level derived from the matched current. A dividing circuit selectively reduces the reference level derived from the first matched current from a first full reference level to a second reduced reference level. The reference circuit is particularly suitable for memory devices having memory cells formed by integrated gate transistors.

Abstract: A memory 200 including an array 201 of rows and columns of memory cells. Row decoder circuitry 211 is provided for selecting in response to a row address a row in array 201 for access. Column decoder circuitry 205 is provided for selecting at least one location within a first group of columns along the selected row in array 201 in response to a column address. At least one shift register 207 is provided for allowing serial access to one of the cells within a second group of columns along the selected row.

Abstract: A semiconductor nonvolatile memory device which is able to be repeatedly rewritten a certain number of times by electrically erasing its memory cells, the semiconductor nonvolatile memory device being comprised of a detecting circuit for detecting if there are any memory cells which had been over-erased (mal-erased) at each rewrite operation, a write circuit for writing, into any cell where over-erasure had been detected, data of a normal or inverted level based on the data which should be written in the over-erased cells, and a recorder for recording if the write circuit wrote the data the same or inverted in level.

Abstract: An integrated circuit (IC) with metal-oxide semiconductor field effect transistor (MOSFET) circuitry and on-chip protection against oxide damage caused by plasma-induced electrical charges includes a MOSFET circuit for receiving and processing an input signal and a complementary MOSFET pass gate coupled to the input thereof for receiving and passing the input signal thereto. The complementary MOSFET pass gate includes complementary MOSFETs with control terminals, input terminals and output terminals, with the control terminals being connected for receiving the IC power supply voltage and ground potentials, the input terminals connected together for receiving the input signal and the output terminals connected together and to the input of the MOSFET circuit for passing the input signal thereto in response to the receiving of the IC power supply voltage and ground potentials.