Abstract: A liquid crystal cell for an image projection apparatus has a liquid crystal layer sandwiched between two conductive layers. The layer surface is divided into one or more regions and one of the sandwiching conductive layers is divided into separate sections each matching a different region. Busbars are bonded on the other of these conductive layers along the edges and boundary lines between adjacent regions (resistors) such that negative and positive writing/erasing can be performed in selected region or regions. By applying one or more current pulses in one or more of these resistors, the corresponding region or regions can be more completely erased and a uniform dark background can be created therein.

Abstract: A dropping resistor and a pair of differential current steering pairs coupled to the resistor with each operable to draw and cease drawing current through the resistor in response to associated corresponding input signals. An integrator is coupled through an emitter follower to one end of the resistor for integrating the current due to the difference in voltage from that voltage established when only one of the pair draws current through the resistor. Preferably the resistor is integrated on a semiconductor chip together with the remainder of the charge pump and integrator circuitry.

Abstract: A driving circuit for driving a cascode bype BiMOS switch which includes a bipolar transistor whose collector is connected through a load to a positive electrode of a power source and a field effect transistor whose drain is connected to an emitter of the bipolar transistor and whose source is connected to a negative electrode of the power source. The driving circuit comprises an n.p series body formed by connecting an n-channel field effect transistor in series relation with a p-channel field effect transistor, wherein a mid-point to the n.p series body is connected to a base of the bipolar transistor. A drain and a source of the n-channel field effect transistor are connected to a D.C. power source and the mid-point, respectively.

Abstract: A memory output circuit which can ensure the sufficient width of output data even in the case of high speed memory operation. The output circuit comprises an output section, a driver circuit for controlling the output section in response to a control signal, and a delay circuit adapted to reset the driver circuit when a predetermined time has elapsed from the enabling of the output section.

Abstract: A projection type liquid crystal display device includes a light source and condenser lenses for emitting two beams of light which are orthogonal to each other. One of the light beams passes through a liquid crystal panel of one color, and the other light beam is further divided into two light beams each of which passes through liquid crystal panels of other colors. The three light beams are then synthesized by dichroic mirrors and fed to a projection lens system.

Abstract: A pulse signal transfer control circuit is located between an input pulse detecting circuit for detecting the arrival of an externally applied input pulse and outputting a pulse signal with a predetermined pulse width, and an R-S flip-flop. The transfer control circuit prohibits the pulse signal from being transferred to the R-S flip-flop during a period in which the R-S flip-flop is set, a period of generation of a first internal clock signal, and a period of generation of a second internal clock signal, and allows the pulse signal to be transferred to the first R-S flip-flop during period in which the first and second clock signals are not generated and the period in which the first R-S flip-flop is reset.

Abstract: A trigger re-synchronization circuit providing reduced trigger gate jitter for use in a high speed display device such as an oscilloscope or digitizer. The trigger re-synchronization circuit is cascadable.

Abstract: A method of driving a liquid crystal display panel which is suitable to display a multivalue image such as a television image or the like, including the steps of inverting an image signal every time a horizontal sync signal is generated, applying the image signal to source lines of the display panel, and synchronously applying an inversion control signal to the common opposite electrode of the display panel, thereby remarkably reducing the driving voltage of the source lines. In this manner, a high-speed CMOS device of a low withstanding voltage can be used as an integrated circuit to drive the source lines.

Abstract: A driver circuit is provided which offers decreased input loading, increased output loading, and a high voltage output level corresponding to a logic-1. These results are achieved through the use of pull-up transistors and capacitive and resistive circuitry which allow bootstrapped voltages.

Abstract: A digital phase-locked loop using a binary overflowing accumulator as a numerically controlled oscillator has external compensation to eliminate frequency-dependent phase offset problems while not requiring any second-order filtering.Operation of the NCO adder initiates with value set by the center frequency control and under the latching action of the latch clocked by the reference oscillator produces a linearly stepped output. Detection of the most-significant bit values produces a square wave at the output. The phase detector latch is used for phase correction, while comparator eliminates steady-state phase error.

Abstract: A CMOS sense amplifier for use in a memory comprises two CMOS differential amplifiers. Each differential amplifier receives the same two signals generated from a selected bit line pair and each provides a different one of a complementary pair of signals. Each differential amplifier has a current mirror for loads. Each differential amplifier uses a transistor current source. A transistor will operate as a more ideal current source if it is in saturation. The transistor current source is biased by the current mirror of the differential amplifier of which it is a part. The resulting differential amplifier thus has a transistor current source which is biased closer to saturation than if biased by a normal clock signal which is either at the high or low power supply voltage. The self-biasing aspect avoids the problems associated with generating a special reference voltage for the differential amplifier.

Abstract: This invention discloses a TTL compatible input buffer which includes means for preventing appreciable current flow into the buffer circuit upon input voltage being supplied to the input signal lead which is substantially above the voltages supplied to the voltage supply terminals of the circuit.

Abstract: A power interface circuit includes a low voltage control chip and a separate, high voltage power chip contained in a common package. The high voltage power chip includes a power switching semiconductor device, such as a thyristor or power MOSFET, and is controlled under the influence of the control chip. Operating power for the low voltage control chip is provided from an auxiliary portion of the high voltage power chip. Such auxiliary portion comprises a voltage regulator, which derives its power from a high voltage lead in the power device. The high voltage lead may comprise a lead on which high voltage power is supplied for power switching purposes. The low voltage control chip may include a high degree of "intelligence", or logic functions, for controlling the power switching device, since the low voltage device may be a microprocessor or other device that can be fabricated with a high density of control elements.

Abstract: A liquid crystal antidazzle mirror for supplying a power to liquid crystal drive control circuit when a key plate is inserted into a key cylinder which comprises a key position detecting switch for detecting that the key plate is inserted into the key cylinder, and an initializing circuit for initializing the liquid crystal drive control circuit to either special mode of predetermined antidazzle or dazzle state upon receiving a detection signal of the key position detecting switch. Thus, the antidazzle mirror can automatically initialize the antidazzle mirror to either special mode of a predetermined antidazzle and dazzle states when power is supplied from a battery.

Abstract: Described is a capacitive structure that can be fabricated with a digital MOS (Metal Oxide Semiconductor) process. The capacitive structure is comprised of two enhancement mode FET devices electrodes connected in series via their gate electrodes. The source and drain electrodes of each FET device are connected together. A third FET device, biased to operate within the linear or resistive region of its characteristic curve, is connected to the gate electrodes of the enhancement mode FET devices. The structure provides a voltage independent capacitor.

Abstract: An integrated logic circuit includes an output circuit for generating an output current which increases linearly in time. In integrated logic circuits the problem presents itself that the rapid variation of the (dis) charging of a data output causes a reverse voltage pulse VL across the inductance formed by the connection wires. The reverse voltage is limited by causing the charge or discharge current (for the load capacities present) to increase linearly to a maximum permissible value. This is done by driving the output field effect transistor with a control voltage VC which varies in time in the form of a square root.

Abstract: An output current control circuit (10) for use with CMOS output buffers so as to reduce significantly ground bounce noise, includes a variable resistance device (28) for limiting the maximum short circuit current in a pull-down transistor (N1) so as to reduce significantly ground bounce noise. A feedback resistor (R.sub.s) is used to sense a reference voltage developed at a system ground reference line (30) for controlling the resistance of the variable resistance device (28).

Abstract: A contour compensating circuit is disclosed for compensating a video signal in such a manner as to obtain contour portions which are not overly stressed.

Abstract: A liquid crystal display having plural liquid crystal cells which are constituted as a matrix, each cell respectively having one transistor and being supplied with image signals by such transistors. The driving circuit for a liquid crystal display of the present invention periodically changes the polarity of the voltage of the image signals and the voltage between both terminals of the liquid crystal cell so as to switch the transistor, and the driving circuit generates gate signals which are impressed on the gate electrode of each transistor, the gate signals having a lowest voltage which is lower than a voltage obtained by subtracting the amplitude voltage of the common electrode of the liquid crystal cells from the lowest voltage in the driving voltage obtained from the image signals.

Abstract: Operating temperature of a liquid crystal cell is controlled by passing heated air on its surface, the heater for the air being operated according to the average temperature of the cell measured by a sensor. Fine control is effected by means of resistive heaters affixed on the exterior surface and by electrodes provided at strategic locations inside to pass current through a conductive layer.