Abstract: A pulse generating circuit is provided for generating a pulse having a time width synchronized with an input pulse and corresponding to a reference voltage. The circuit is particularly designed not to be affected by parasitic capacitance. A circuit for charging one electrode of an integrating circuit with a constant current is controlled by turning on or off a switch in response to the input pulse. The other electrode of the integrating capacitor is connected with a reference voltage source by driving a switch in response to a pulse having a pulse width which contains the time period of the input pulse and which is wider than the input pulse. A comparator is provided for comparing the potential at one electrode of the integrating capacitor and ground potential. A desired pulse is generated by a logic circuit which is receives both the output of the comparator and the input pulse.

Abstract: The present invention provdes a circuit for driving a TTL bus from an ECL circuit. The circuit of the present invention speeds up the "tri-state" to "active" transition by eliminating the need to pass the tri-state signal through a translator and buffer. A tri-state control circuit accepts true ECL input directly, thus eliminating the delay, power and density "cost" of the translator and buffer circuits. This circuit further improves the delay performance of tri-state/active transitions by restricting device saturation to low levels.

Abstract: A switching circuit is described, for selecting between first and second clock signals. When it is desired to switch from the first to the second clock signal, the first clock signal is de-selected in synchronism with the beat of the first clock and then, after a delay, the second clock signal is selected in synchronism with the beat of the second clock. Conversely, when it is desired to switch from the second to the first clock signal, the second clock signal is de-selected in synchronism with the beat of the second clock and then, after a delay, the first clock signal is selected in synchronism with the beat of the first clock. This avoids the possibility of a short pulse or "glitch" at the instant of switch-over.

Abstract: A circuit responsive to a switching signal for dynamically changing the frequency source of a system clock. The circuit allows addition of new frequency sources without substantial changes to the circuit because its circuitry for detecting an inactive cycle period of the new frequency source is asynchronous (i.e. not clocked by the new frequency source).

Abstract: An interconnection circuit of a semiconductor integrated circuit connected between a first circuit (41) for applying an input signal and the second circuit (44) for outputting an output signal to the other circuit comprises circuits of input stage, processing stage and output stage. The circuit of the input stage comprises an n channel MOS field effect transistor (14) and a resistance (7). The circuit of the processing stage comprises two CMOS inverters (1, 2, 31, 32). The circuit of the output stage comprises a CMOS inverter (15, 16) and a series connection of a resistance (21), an npn bipolar transistor (17) and an n channel MOS filed effect transistor (18). When an overvoltage is applied to the input terminal (8), the circuit of the input stage protects the circuit by a parasitic diode (25) formed by the transistor (14) or the punch through phenomenon of the transistor (14). When the power supply V.sub.

Abstract: A diffraction grating responds to incoming radiation incident thereon within a given range of incidence angles and re-directs such incident radiation from the structure in a selected direction within relatively limited confines. A liquid crystal material is positioned in contact with the diffracting surface of said at least one diffraction structure, the liquid crystal material, when inactivated, having a refractive index substantially the same as that of the diffraction structure. Activation means place the liquid crystal material in an activated state so that the refractive index thereof is substantially different from that of the diffraction structure whereby incoming radiation within a given range of incidence angles is transmitted through the structure and exits in the selected direction.

Abstract: There is an R-S flip-flop circuit having a threshold voltage of a first value. An input terminal of a Schmitt trigger circuit having a second threshold voltage of a lower value than the first value and a third threshold voltage of a higher value than the first value is connected to an output terminal of the R-S flip-flop circuit.

Abstract: Provided is a modulator having two amplifying stages for supplying high-voltage pulses to the primary winding of a transformer connected to a microwave transmitter tube. The first stage uses field-effect transistors connected in a common source configuration to amplify input pulses to drive the second stage, which uses field-effect transistors connected in a common gate configuration to drive the transformer. The circuit configuration provides a large voltage swing across the transformer primary and a short transistor switching time.

Abstract: A circuit (40) constructed in accordance with this invention includes a ring oscillator (25) to provide a signal which is dependent on the propagation delays of the inverters (33, 34, 35) comprising the ring oscillator, therefore the frequency of the ring oscillator is inversely dependent upon the propagation delays of the inverter comprising the ring oscillator. Means (37) are provided to determine the propagation delay introduced by the components in the ring oscillator by measuring the frequency of the output signal produced by the ring oscillator which provides a signal to a multiplexer (36) which selects among a number of preset delay components (26) those components which are necessary to ensure that the propagation delay caused by the circuitry (not shown) connected to the input lead (21) of the circuit constructed in accordance with this invention plus the propagation delay introduced by the selectable delay elements is nearly a constant propagation delay.

Abstract: A monostable circuit responsive conditionally to a circuit input signal for generating a circuit output signal having a pulse of a predetermined duration includes an AND gate having two input ports and an output port. ONe of the input ports is coupled to the circuit input signal and inverts that signal. The other of the input ports is coupled to the circuit output signal. A reset OR gate receives a reset signal and the output of the AND gate. When the reset signal is low, the reset OR gate outputs the output of the AND gate, thus enabling the curcuit. The output of the reset OR gate also goes to a ramp generator having a ramp capacitor, the charging current to which is provided by a current driver. The reference voltage for a comparator is provided by circuitry identical to that associated with the ramp capacitor except that an intermediate bias reference is applied to it. This bias reference is compensated for the effect temperature changes on the circuit.

Abstract: The process for the detection of an eddy current-induced body in the action range of an inductive resonant circuit component (L) uses in place of a continuous operation and detection of the current change, a network containing a resonant circuit (L,C) is briefly excited with an electric function and the system response of the network is evaluated. The proximity sensor is constituted by an oscillatable network (L,C) operated on the input side with a function generator and, on the output side, the system response is investigated with an evaluation circuit.

Abstract: A sense amplifier for use in a CMOS static random access memory. The core of the sense amplifier comprises seven transistors: two sensing transistors with their sources coupled to a common pull down node, a pull down transistor for drawing current from the pull down node during sensing operations, and a four transistor latch coupled to the drains of the two sensing transistors. The four transistor latch comprises two cross coupled CMOS inverters. When the pull down transistor is activated, the four transistor latch automatically amplifies the voltage differential on the gates of the two sensing transistors, typically latching in less than two nanoseconds. Since the latch is made up of CMOS inverters, no d.c. current is drawn by the sense amplifier after the input data has been sensed and latched. As a result, relatively powerful transistors can be used in the sense amplifier.

Abstract: A controlled CMOS substrate voltage generator generates a rectangular wave pulse which is supplied to the pumping circuit by a pumping capacitor and controlled decoupling members. At the same time the decoupling members are activated by a control circuit and are completely opened, so that the full pumping lift is completely utilized without reduction due to threshold voltages. In order to reduce the injection of charge carriers of nCMOS decoupling members, inversely activated pMOS decoupling members, which are strongly conducting at low substrate bias voltage near 0V, are connected in parallel to the latter. To increase performance, the circuit is designed as a circuit in phase opposition. Improved sensors are provided, which during the active phase maintain the shift of the substrate voltage produced upon wobble of the bit strings toward more negative values by alternation of the reference voltage of the sensor.

Abstract: An improved comparator circuit which can operate stably against noise or fluctuation in a power supply is disclosed. The comparator circuit includes a differential amplifier having first and second input terminal, a first diode for biasing the first input terminal at a constant voltage, a second diode coupled between the first and second input terminals, and means for gradually changing the potential at the first input terminal towards the above constant voltage.

Abstract: An overlay for an electronic circuit used as a diagnostic apparatus and a method of conducting the diagnosis using the overlay. A plurality of temperature sensitive areas which are made from encapsulated liquid crystal zones are positioned on the overlay in accordance with the spatial configuration of the electronic components with which the overlay is to be used. Each of the temperature sensitive areas is aligned with a respective component on the electronic circuit and each of the liquid crystal zones has a first color identical to the color of the rest of the crystals when the respective electronic components are within a predetermined temperature range. When the temperature of a component changes by a certain quantity, the color of the crystal zone also changes, which change is visually observed.

Abstract: A detection system for a sliding lift or elevator door comprises at least two sensors for monitoring the door opening. The sensors are arranged to detect the presence of a moving irregular shape (e.g. human form) in the doorway to reverse the opening action of the door or, if already open, to prevent the door from closing. A signal compensation circuit is provided to process the output signals from the sensors in a sense to maintain the outputs equal under steady state conditions. This is achieved by using the output of a first sensor as a reference signal. A comparator compares the output of a second sensor with a reference signal and through a feedback loop modifies the output of the said second sensor in a sense to equal the output of the first sensor. The feedback loop contains a delay circuit which is switchable between a long and a short delay. For slow changes in the output of the second sensor the long delay is effective but for first changes the delay circuit is switched to provide a short delay.

Abstract: A synchronizer is comprised of a voltage amplifier having an input terminal for receiving a voltage sample and an output terminal for generating an output voltage that is inversely proportional to the voltage of the input terminal. Also, a first feedback circuit couples the output terminal to a control transistor internal to the amplifier, and a second feedback circuit couples the output terminal to the input terminal. The first feedback circuit together with the control transistor has a fast response time, in comparison to the second feedback circuit; and it operates to quickly increase the output voltage when the voltage sample on the input terminal is below a predetermined level, and vice versa, without altering the voltage sample on the input terminal. And, the second feedback circuit operates to slowly modify the voltage sample on the input terminal in inverse proportion to the output terminal voltage.

Abstract: A high voltage power transistor circuit composed of a pair of transistors (TR1, TR2) serially connected through an inductor (L) to a supply voltage. Associated components are connected to the transistors which determine various periods of operation. In order to ensure that the transistors (TR1, TR2) are rendered non-conducting simultaneously, sensors (S1, S2) sense their change in base current to produce pulses in monostable multivibrators (M1, M2) whose relative phases are compared in a digital phase comparator (PC). The drive for each transistor (TR1, TR2) is provided by an associated driver stage (DR1, DR2) via an associated device (DC1, DC2) having a characteristic used to control the cut-off of its associated transistor. One of the devices (DC2) has a variable characteristic which is controlled by the output of the phase comparator (PC) to ensure the required simultaneous non-conduction of the transistors.

Abstract: A squaring circuit (FIG. 1, 100; FIG. 3, 300) includes an operational amplifier (10) having its positive input terminal connected to ground, its negative input terminal connected through a nonlinear voltage-to-current conversion device (FIG. 1, T.sub.2, T.sub.3 ; FIG. 3, M.sub.1, M.sub.2, T.sub.2) to a balanced source of the input voltage (.+-.V.sub.IN), and its output terminal connected through a linear current-to-voltage conversion device (FIG. 1, R.sub.1 ; FIG. 3, T.sub.1, C.sub.1) to its negative input terminal. The circuit can be made to have a balanced output (FIGS. 2 and 5), and the circuit can be made in the configuration of either a continuous-time circuit (FIGS. 1 and 2) or a sampled-data circuit (FIGS. 3 and 5).

Abstract: A fault tolerant logic circuit capable of absorbing many D.C. and A.C. defects. The logic circuit employs a number of redundant logic gate circuits. The gate circuits are arranged in at least first and second interconnected signal paths. The logic gate circuits have two independent outputs. The two independent outputs are each connected to an input in a discrete one the first and second interconnected signal paths.