Abstract: A radiological installation with dynamic compensation in the optical path of the image, with an optical attenuator with locally adjustable transmission placed at least in the vicinity of a focal plane in which the radiological image is formed situated upstream of the television camera of the image acquisition chain.

Abstract: In the present invention, a first arm piece for fixing a liquid crystal display element and a second arm piece for fixing a reflecting plate are interconnected at their base portions to form a frame, and a printed circuit board which carries thereon a liquid crystal display element driving circuit connected electrically to the liquid crystal display element is fixed to the back of the reflecting plate, in which construction the angle between the liquid crystal display element and the reflecting plate can be set and maintained stably. Further, a light conductor is disposed on a rear face side of the liquid crystal display element and a light transmission control member is disposed on a rear surface of the light conductor whereby an internal light emitted from an internal light source for illumination of the liquid crystal display element is prevented from leaking to the observer side, that is, it can be conducted in a direction not obstructing the observer's sight.

Abstract: A driver for transmitting a digital differential signal along a transmission line during a packet time and not during an idle time while maintaining a constant common voltage between the transmission line and ground throughout the packet and idle time periods. A driving circuit and its drive controller in the driver and respectively formed from paired matched transistors which function as on-off switching circuits and have a common emitter load acting as a constant current source. A collector of a first transistor in the drive controller is connected to the common emitter of the driving circuit and a collector of a second transistor in the drive controller is respectively connected to the collectors of the pair of transistors of the driving circuit through respective matched diodes.

Abstract: An adjustable RMS circuit for an input signal is first compressed by use of a bipolar logarithmic converter. The low-level, high-frequency accuracy of the converter may be improved by increasing its gain in response to the presence of such components. An inverted half wave rectified signal derived from the compressed signal is then combined with a half intensity signal derived from the compressed signal to produce a signal which is substantially equal to the absolute value of the compressed signal. A reference signal of variably selectable level is further combined with the combined signal to provide an output signal offset to a desired threshold level.

Abstract: A semiconductor integrated circuit device including: a first transistor whose base receives an input signal, and whose collector is connected to a high power supply voltage; a second transistor whose base is conducted to the emitter of said first transistor and whose emitter is connected to a low power supply voltage; a third transistor whose base is connected to the collector of said first transistor, whose collector is connected to said high power supply voltage, and whose emitter is connected to the collector of said second transistor directly or via a load element; and a fourth transistor whose base is connected to the emitter of said third transistor, whose emitter is connected to said low power supply voltage, and from whose collector an output signal of said semiconductor integrated circuit device is taken out.

Abstract: A liquid crystal display of the active matrix type includes a plurality of row electrodes orthogonal with a row of column electrodes and between each crosspoint is included a series arrangement of a liquid crystal element and a non-linear resistance provided by a parallel pair of oppositely poled diodes. Each of the diodes is constructed to have its photosensitive layer shielded from ambient light by its two electrodes, one of which is larger in cross-section than the light-sensitive layer and the other of which wraps around the edges of the layer.

Abstract: In a circuit for driving a MOSFET connected to a load on the source terminal, the MOSFET is configurated as a source follower that is driven by a voltage doubling circuit including two diodes (D1, D2) serially connected together. The drain terminal of the MOSFET is connected to the operating voltage source and its gate terminal to the voltage doubling circuit which includes a capacitor (C). One terminal of the capacitor is connected between the diodes and its other terminal is supplied with a clocked dc voltage. The first diode (D2) is formed by a lateral MOSFET, whose gate electrode is connected with the drain zone. The second diode is formed by a vertical bipolar transistor with low current gain. A resistor is located between the emitter zone and the source zone. This particular circuit geometry is readily suitable for realization in integrated form.

Abstract: A circuit (40) constructed in accordance with this invention includes a ring oscillator (25) to provide a signal which is dependent on the propagation delays of the inverters (33, 34, 35) comprising the ring oscillator, therefore the frequency of the ring oscillator is inversely dependent upon the propagation delays of the inverter comprising the ring oscillator. Means (37) are provided to determine the propagation delay introduced by the components in the ring oscillator by measuring the frequency of the output signal produced by the ring oscillator which provides a signal to a multiplexer (36) which selects among a number of preset delay components (26) those components which are necessary to ensure that the propagation delay caused by the circuitry (not shown) connected to the input lead (21) of the circuit constructed in accordance with this invention plus the propagation delay introduced by the selectable delay elements is nearly a constant propagation delay.

Abstract: A control circuit having a slow-start section is enabled to carry out its expected, principal function(s) only after the voltage at the slow-start section input has reached a certain level. The system assures that a delay interval in control circuit operation is measured from the time devices within the circuit's internal voltage supply become effective to deliver voltage levels sufficient to allow the circuit to perform the principal function. A delay network is connected across a device of the internal voltage supply, which otherwise supplies an operating voltage level to the control circuit.

Abstract: A circuit arrangement for reducing the settling time of amplifiers to which photoelectronic components are connected. A control circuit is provided which, operating in conjunction with components of this circuit arrangement, prevents the parasitic capacitance of the photoelectronic component from being charged up when the circuit arrangement is connected to the operating voltage.

Abstract: This charge pump circuit comprises a capacitor connected with a first terminal thereof to a reference voltage point through a first switch element and with a second terminal thereof to a switching section. The switching section, which is arranged between a positive supply voltage line and the ground, is controlled so as to alternately and selectively connect the second terminal of the capacitor to the positive supply and to ground. The first terminal of the capacitor is further connected to the gate of the MOS transistor to be driven. During operation the switch section is controlled so as to alternately charge the capacitor and allow transfer of the charge of the capacitor to the MOS transistor gate, thereby achieving a fast charging of the MOS transistor and a low circuit dissipation in the DC mode.

Abstract: A sense amplifier circuit operable at high speed, but having reduced power dissipation. The amplifier has two input lines, each receiving a respective voltage that differs from the other. A differential amplifier is connected between sources of high and low voltage levels and also has a pair of input terminals respectively connected to the first and second input lines. The amplifier also has first and second inverters, each having an input terminal and an output terminal, the input terminal of the first inverter being connected to the first input line and the input terminal of the second inverter being connected to the second input line. A first series combination of at least two transistors is provided between the first input line and the source of low level voltage, one of the two transistors having a control terminal connected to the output terminal of the first inverter.

Abstract: An input signal is applied to first and second logic gates to produce a first output out-of-phase with the input signal and a second output in-phase with the input signal. The first and second outputs are applied to a set/reset flip-flop whose output is applied to a transition detector to produce pulses having a minimum width when the input signal changes level for longer than some predetermined period Tl. The first and second logic gates are designed to have asymmetrical responses whereby input pulses of either polarity having less than the predetermined width Tl are treated as "noise spikes", are effectively filtered from the system, and do not cause a change in the state of the set/reset flip-flop.

Abstract: A circuit for producing output pulses in response to an alternating signal supplied to the input thereof which is comprised of a pair of complementary transistors cascoded between a pair of current mirror circuits which source and sink currents to and from a common terminal respectively. The alternating input signal is applied to the interconnected emitters of the two transistors thereby rendering one more conductive while the other is rendered less conductive and vice versa. The currents which are sourced or sunk at the common terminal are proportional to the currents flowing in the two transistors and are compared to cause an output transistor to switch operating states thereby producing the output pulse.

Abstract: A liquid crystal device having a cell structure including two base plates each provided with transparent electrodes and a the ferroelectric liquid crystal disposed between the base plates. Adjacent to the transparent electrodes, auxiliary electrodes ordinarily composed of a metal are disposed so as to lower the resistance of the transparent electrodes. Insulating films are also disposed alternately with the auxiliary electrodes so as to provide a flat surface, whereby generally flat surfaces contacting the ferroelectric liquid crystal are formed to provide a uniform monodomain free of alignment defects. Thus, proper driving characteristics of ferroelectric liquid crystal device are provided.

Abstract: An improved EFL gate which provides concurrent true and complementary outputs. An input transistor has its base coupled to an input and its emitter coupled to an emitter of a reference transistor. The reference transistor has its base coupled to a voltage reference and its collector coupled to the base of a true output transistor. The emitter of the true output transistor provides the true output, while its collector is coupled to a voltage supply. A complementary output transistor has its base coupled to the collector of the input transistor with its emitter providing the complementary output. Its collector is coupled to the voltage supply, as is the collector of the input transistor.

Abstract: A switchable color filter employs chiral liquid crystal circular polarizers to minimize the attenuation of light passing through a system in which it is incorporated. One preferred embodiment (12) of the switchable color filter includes a light modulator (32) positioned between the light polarizing assembly (20) and first and second chiral liquid crystal cells (36 and 38). The light polarizing assembly receives unpolarized light and transmits circularly polarized light of colors included within first and second narrow color bands. The first chiral cell reflects incident light within the first color band and in a first polarization state, and the second chiral cell reflects incident light within the second color band and in a second polarization state. The light modulator cooperates with a switching circuit (34) to selectively provide first and second polarization switching states.

Abstract: A semiconductor circuit of a current mode type logic is provided having a reference voltage generating circuit which generates the reference voltage to be applied to the logic circuit in response to a clock signal to latch the state corresponding to an input signal at an instant of the clock signal input. The reference voltage has three levels in response to the voltage levels of the clock signal and the input signal: a middle voltage between the two high and low voltage levels of the input signal when the clock signal is at a first level voltage; a voltage higher than the high voltage level of the input signal when the clock signal is at a second level voltage and the output signal is at a high voltage; and a voltage lower than the low voltage level of the input signal when the clock signal is at a second level voltage and the output signal is at a second level voltage and the output signal is at a low voltage.

Abstract: A display device, such as an LCD, has alignment layers made of different materials; thus one layer can have a low curing temperature so as not to cause damage to delicate organic layers, such as a color filter, during curing, while the other layer can have a larger tilt angle so as to minimize ambiguities in the liquid crystal material.

Abstract: An active matrix liquid crystal display device has a plurality of display electrodes arranged in a matrix array and selectable through control of thin film transistors for application of voltage between selected display electrodes and a common electrode to obtain image display. Each thin film transistor has a semiconductive layer and a gate insulating film both formed to have the same pattern. Each thin film transistor has a gate electrode formed on the gate insulating film with the edges of the gate electrode inwardly spaced apart from the corresponding edges of the gate insulating film. The semiconductor layer and gate insulating film have extensions extending under a corresponding gate bus.