Patents Examined by Tu-Tu Ho
  • Patent number: 10167188
    Abstract: A micro-electro-mechanical system (MEMS) transducer including an enclosure defining an interior space and having an acoustic port formed through at least one side of the enclosure. The transducer further including a compliant member positioned within the interior space and acoustically coupled to the acoustic port, the compliant member being configured to vibrate in response to an acoustic input. A back plate is further positioned within the interior space, the back plate being positioned along one side of the compliant member in a fixed position. A filter is positioned between the compliant member and the acoustic port, and the filter includes a plurality of axially oriented pathways and a plurality of laterally oriented pathways which are acoustically interconnected and dimensioned to prevent passage of a particle from the acoustic port to the compliant member.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: January 1, 2019
    Assignee: Apple Inc.
    Inventors: Janhavi S. Agashe, Anthony D. Minervini, Ruchir M. Dave, Jae H. Lee
  • Patent number: 10157913
    Abstract: A method of forming an array comprising pairs of vertically opposed capacitors comprises forming an upwardly-open conductive lining in individual capacitor openings in insulative-comprising material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed radially inward of the upper and lower capacitor electrode linings in the individual capacitor openings. Conductive material is formed radially inward of the capacitor insulator in the individual capacitor openings and elevationally between the capacitor electrode linings. The conductive material is formed to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Additional methods and structure independent of method are disclosed.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 10157987
    Abstract: Fin-based well straps are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a FinFET disposed over a doped region of a first type dopant. The FinFET includes a first fin structure doped with a first dopant concentration of the first type dopant and first source/drain features of a second type dopant. The IC device further includes a fin-based well strap disposed over the doped region of the first type dopant. The fin-based well strap connects the doped region to a voltage. The fin-based well strap includes a second fin structure doped with a second dopant concentration of the first type dopant and second source/drain features of the first type dopant. The second dopant concentration is greater than (for example, at least three times greater than) the first dopant concentration.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10149032
    Abstract: A micro-electro-mechanical system (MEMS) transducer including an enclosure defining an interior space and having an acoustic port formed through at least one side of the enclosure. The transducer further including a compliant member positioned within the interior space and acoustically coupled to the acoustic port, the compliant member being configured to vibrate in response to an acoustic input. A back plate is further positioned within the interior space, the back plate being positioned along one side of the compliant member in a fixed position. A filter is positioned between the compliant member and the acoustic port, and the filter includes a plurality of axially oriented pathways and a plurality of laterally oriented pathways which are acoustically interconnected and dimensioned to prevent passage of a particle from the acoustic port to the compliant member.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: December 4, 2018
    Assignee: Apple Inc.
    Inventors: Janhavi S. Agashe, Anthony D. Minervini, Ruchir M. Dave, Jae H. Lee
  • Patent number: 10145518
    Abstract: The present invention relates to a nano-scale light emitting diode (LED) electrode assembly emitting polarized light, a method of manufacturing the same, and a polarized LED lamp having the same, and more particularly, to a nano-scale LED electrode assembly in which partially polarized light close to light that is linearly polarized having one direction is emitted as an emitted light when applying a driving voltage to the nano-scale LED electrode assembly and also nano-scale LED devices are connected to a nano-scale electrode without defects such as an electrical short circuit while maximizing a light extraction efficiency, a method of manufacturing the same, and a polarized LED lamp having the same.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: December 4, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Rag Do, Yeon Goog Sung
  • Patent number: 10134657
    Abstract: A process comprises bonding a semiconductor wafer to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer is transparent. After the bonding, a damage track is formed in the inorganic wafer using a laser that emits the wavelength of light. The damage track in the inorganic wafer is enlarged to form a hole through the inorganic wafer by etching. The hole terminates at an interface between the semiconductor wafer and the inorganic wafer. An article is also provided, comprising a semiconductor wafer bonded to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer is transparent. The inorganic wafer has a hole formed through the inorganic wafer. The hole terminates at an interface between the semiconductor wafer and the inorganic wafer.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: November 20, 2018
    Assignee: Corning Incorporated
    Inventors: Daniel Wayne Levesque, Jr., Garrett Andrew Piech, Aric Bruce Shorey
  • Patent number: 10128248
    Abstract: An apparatus is provided which comprises: a stack of transistors of a same conductivity type, the stack including a first transistor and a second transistor coupled in series and having a common node; and a feedback transistor of the same conductivity type coupled to the common node and a gate terminal of the first transistor of the stack.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Karthik Ns, Dharmaray Nedalgi, Vani Deshpande, Leonhard Heiss, Amit Kumar Srivastava
  • Patent number: 10121739
    Abstract: A semiconductor device comprising first and second dies is provided. The first die includes a first through-substrate via (TSV) extending at least substantially through the first die and a first substantially helical conductor disposed around the first TSV. The second die includes a second TSV coupled to the first TSV and a second substantially helical conductor disposed around the second TSV. The first substantially helical conductor is configured to induce a change in a magnetic field in the first and second TSVs in response to a first changing current in the first substantially helical conductor, and the second substantially helical conductor is configured to have a second changing current induced therein in response to the change in the magnetic field in the second TSV.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kyle K. Kirby
  • Patent number: 10121714
    Abstract: A semiconductor device includes a box-shaped casing including a ceiling wall with a first window, a semiconductor chip having an output electrode and assembled in the casing, a first conductive block disposed in the casing, and a first connection terminal being bent so as to implement an elongated U-shape. The semiconductor device is adapted for electrical connection to a circuit board having a first land. The circuit board is placed on the ceiling wall. The first window is at a position corresponding to the first land. A lower end of the first conductive block is connected to a surface of the output electrode and the first connection terminal contacts to the first conductive block.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 6, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Kousuke Komatsu
  • Patent number: 10121894
    Abstract: In an LDMOS having an element isolation region of an STI structure, there is prevented an occurrence of insulation breakdown which might be caused when electrons generated in a semiconductor substrate near an edge portion of a bottom face of the element isolation region are poured into a gate electrode. Immediately over an upper surface of an offset region adjacent to the element isolation region embedded in a main surface of the semiconductor substrate between a source region and a drain region, there is provided a trench penetrating a silicon film forming the gate electrode. As a consequence, the silicon film and a metal film for filling the trench form the gate electrode.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: November 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Katsumi Eikyu, Atsushi Sakai
  • Patent number: 10121675
    Abstract: In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate, source/drain epitaxial layers disposed between two adjacent gate structures, and an etching-stop layer (ESL) covering the source/drain epitaxial layers. An opening is formed in the ILD layer by etching. A dielectric filling layer is formed in the opening. By using wet etching, the ILD layer disposed above the source/drain epitaxial layers is removed. The ESL disposed on the source/drain epitaxial layers is removed, thereby at least partially exposing the source/drain epitaxial layers. A conductive material is formed over the exposed source/drain epitaxial layers.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: November 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 10115791
    Abstract: An embodiment of a semiconductor device includes a body region of a first conductivity type in a SiC semiconductor body of a second conductivity type. A super junction structure is in the SiC semiconductor body, and includes a drift zone section being of the second conductivity type and a compensation structure of the first conductivity type. The compensation structure adjoins the body region and includes compensation sub-structures consecutively arranged along a vertical direction perpendicular to a surface of the SiC semiconductor body. The compensation sub-structures include a first compensation sub-structure and a second compensation sub-structure. A resistance of the second compensation sub-structure between opposite ends of the second compensation sub-structure along the vertical direction is at least five times larger than a resistance of the first compensation sub-structure between opposite ends of the first compensation sub-structure along the vertical direction.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: October 30, 2018
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Rudolf Elpelt, Dethard Peters
  • Patent number: 10109521
    Abstract: A method of forming hybrid Co and Cu CA/CB contacts and the resulting device are provided. Embodiments include forming a forming a plurality of trenches through an ILD down to a substrate; forming a first metal liner on side and bottom surfaces of each trench and over the ILD; annealing the first metal liner; forming a second metal liner over the first metal liner; forming a first plating layer over a portion of the second metal liner in each trench; forming a second plating layer over the second metal liner and first plating layer in a remaining portion of each trench, the first and second plating layers being different materials; and planarizing the second plating layer and the second and first metal liners down to the ILD.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Qiang Fang, Shafaat Ahmed, Changhong Wu, Zhiguo Sun, Jiehui Shu
  • Patent number: 10109665
    Abstract: A semiconductor device includes a semiconductor substrate with first and second surfaces facing each other, an etch stop pattern in a trench formed in the first surface of the semiconductor substrate, a first insulating layer on the first surface of the semiconductor substrate, and a through via penetrating the semiconductor substrate and the first insulating layer. The etch stop pattern surrounds a portion of a lateral surface of the through via.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: October 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jin Lee, Kwangjin Moon, Seokho Kim, Sukchul Bang, Jin Ho An, Naein Lee
  • Patent number: 10096743
    Abstract: Provided are Gigantic quantum dots and a method of forming gigantic quantum dots. Each of the gigantic quantum dots includes a core constituted of CdSe, a shell constituted of ZnS, and an alloy configured between the core and the shell. The core is wrapped by the shell. The alloy constituted of Cd, Se, Zn and S, wherein a content of the Cd and Se gradually decreases from the core to the shell and a content of the Zn and S gradually increases from the core to the shell. A particle size of each of the gigantic quantum dots is equal to or more than 10 nm.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 9, 2018
    Assignee: Unique Materials Co., Ltd.
    Inventors: Pi-Tai Chou, Shang-Wei Chou, Yu-Min Lin, Chin-Cheng Chiang, Chia-Chun Hsieh
  • Patent number: 10096537
    Abstract: Embodiments of the present invention are directed to heat transfer arrays, cold plates including heat transfer arrays along with inlets and outlets, and thermal management systems including cold-plates, pumps and heat exchangers. These devices and systems may be used to provide thermal management or cooling of semiconductor devices and particularly such devices that produce high heat concentrations. The heat transfer arrays may include microjets, microchannels, fins, and even integrated microjets and fins. Other embodiments of the invention are directed to heat spreaders (e.g. heat pipes or vapor chambers) that provide enhanced thermal management via enhanced wicking structures and/or vapor creation and flow structures. Other embodiments provide enhanced methods for making such arrays and spreaders.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 9, 2018
    Assignee: Microfabrica Inc.
    Inventors: Richard T. Chen, Will J. Tan
  • Patent number: 10096655
    Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli
  • Patent number: 10090338
    Abstract: Disclosed is a method for manufacturing an array substrate, the array substrate and a display device which can reduce manufacturing steps of a color filter process and further reduce manufacturing steps of the display device, thereby saving manufacturing cost and time. The method for manufacturing the array substrate includes: forming a thin film transistor on a base substrate; forming a passivation layer having a via hole on a front side of the thin film transistor and forming a photo spacer on a front side of the passivation layer through a halftone mask patterning process. With this method for manufacturing the array substrate, there is no need to prepare the photo spacer on a back side of the color filter substrate. Therefore, it is possible to reduce manufacturing steps of a color filter process, which in turn further reduces manufacturing steps of the display device, thereby saving manufacturing cost and time.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: October 2, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Shifei Shen, Jeong Hun Rhee, Youngjin Song, Maomao Fang, Jianxin Hou
  • Patent number: 10090335
    Abstract: Disclosed is a light emitting diode display device in which a process time taken in a process of connecting a light emitting device to a pixel circuit is shortened. The light emitting diode display device includes a pixel including a driving thin film transistor (TFT) on a substrate, a first planarization layer covering the pixel, a concave portion in the first planarization layer, a light emitting device in the concave portion and including a first electrode and a second electrode, a second planarization layer covering the first planarization layer and the light emitting device, a pixel electrode electrically connected to the driving TFT and the first electrode of the light emitting device, and a common electrode electrically connected to the second electrode of the light emitting device. The pixel electrode and the common electrode are on the second planarization layer.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: October 2, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: HanSaem Kang, HyeonHo Son
  • Patent number: 10083890
    Abstract: Aligned high quality boron nitride nanotubes (BNNTs) can be incorporated into groups and bundles and placed in electronic and electrical components (ECs) to enhance the heat removal and diminish the heat production. High quality BNNTs are excellent conductors of heat at the nano scale. High quality BNNTs are electrically insulating and can reduce dielectric heating. The BNNTs composite well with a broad range of ceramics, metals, polymers, epoxies and thermal greases thereby providing great flexibility in the design of ECs with improved thermal management. Controlling the alignment of the BNNTs both with respect to each other and the surfaces and layers of the ECs provides the preferred embodiments for ECs.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: September 25, 2018
    Assignee: BNNT, LLC
    Inventors: R. Roy Whitney, Kevin C. Jordan, Michael W. Smith, Jonathan C. Stevens