Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to one or more barrier layers having various characteristics formed under and/or over and/or around correlated electron material.

Abstract: A 3D semiconductor device, the device including: a first die including a first transistors layer and a first interconnection layer; and a second die overlaying the first die, the second die including a second transistors layer and a second interconnection layer, where the second die thickness is less than 2 microns, and where the first die is substantially larger than the second die.

Abstract: Determining a modal amplitude of an inhomogeneous field includes: preparing an initial entangled state of a quantum sensor; subjecting the quantum sensor to the inhomogeneous field of the analyte; subjecting a first qudit sensor of the quantum sensor to a first perturbation pulse; receiving the first perturbation pulse by the first qudit sensor to prepare a first intermediate entangled state of the quantum sensor, the first intermediate entangled state comprising a first intermediate linear superposition; changing the initial linear superposition to the first intermediate linear superposition in response to receiving the first perturbation pulse by the quantum sensor; and determining a final entangled state of the quantum sensor after applying the first perturbation pulse to determine the modal amplitude of the inhomogeneous field of the analyte.

Abstract: Embodiments generally relate to chips containing one or more hermetically sealed chambers that may be dismantled under controlled conditions using a release technique. In one embodiment a chip comprises a first hermetic seal bonding first and second elements to create a first chamber and a second hermetic seal bonding third and fourth elements to create a second chamber encompassing the first chamber. The first hermetic seal may be broken open independently of the second hermetic seal by the application of a mechanical or thermal technique.

Abstract: The instant disclosure provides an optical component packaging structure which includes a far-infrared sensor chip, a first metal layer, a packaging housing and a covering member. The far-infrared sensor chip includes a semiconductor substrate and a semiconductor stack structure. The semiconductor substrate has a first surface, a second surface which is opposite to the first surface, and a cavity. The semiconductor stack structure is disposed on the first surface of the semiconductor substrate, and a part of the semiconductor stack structure is located above the cavity. The first metal layer is disposed on the second surface of the semiconductor substrate, the packaging housing is used to encapsulate the far-infrared sensor chip and expose at least a part of the far-infrared sensor chip, and the covering member is disposed above the semiconductor stack structure.

Abstract: Circuits and antennas integrated in dies and corresponding method. The circuits and the antennas are positioned on the front surface and the back surface of the substrate respectively, but both are electrically coupled to the shared ground of the substrate. To maintain the mechanical strength of the die, some dummy metals are positioned on the back surface of the substrate and positioned around but separated away the antennas. Further, to reduce the potential side effects induced by the induced current, some ground balls are positioned on one or surfaces of the substrate.

Abstract: A semiconductor package includes a substrate, a plurality of semiconductor chips stacked on the substrate, and a plurality of bonding layers bonded to lower surfaces of the plurality of semiconductor chips. The plurality of bonding layers may be divided into a plurality of groups, each having different physical properties depending on a distance from the substrate.

Abstract: According to one embodiment, a method for manufacturing an LED device includes forming a laminated semiconductor layer including a GaN layer of a first conductivity type, a GaN-based luminous layer, and a GaN layer of a second conductivity type stacked in this order on a surface of a substrate, forming a resist pattern on the laminated semiconductor layer, subjecting the laminated semiconductor layer to reactive ion etching using the resist pattern as a mask to selectively remove the laminated semiconductor layer to form an LED element structure part and an electrode connection region, removing the resist pattern, and treating the substrate including the LED element structure part and the electrode connection region with a first etching residue removing aqueous solution.

Abstract: A semiconductor package structure includes a base. A first die is mounted on the base. The first die includes a plurality of first pads arranged in a first tier, and a plurality of second pads arranged in a second tier. A second die is mounted on the base and includes a plurality of third pads with the first pad area, and a plurality of fourth pads with the second pad area, alternately arranged in a third tier. The second die also includes a first bonding wire having two terminals respectively coupled to one of the first pads and one of the fourth pads. The semiconductor package structure also includes a second bonding wire having two terminals respectively coupled to one of the third pads and one of the second pads.

Abstract: A method of forming vertical fin field effect transistors, including, forming a silicon-germanium cap layer on a substrate, forming at least four vertical fins and silicon-germanium caps from the silicon-germanium cap layer and the substrate, where at least two of the at least four vertical fins is in a first subset and at least two of the at least four vertical fins is in a second subset, forming a silicon-germanium doping layer on the plurality of vertical fins and silicon-germanium caps, removing the silicon-germanium doping layer from the at least two of the at least four vertical fins in the second subset, and removing the silicon-germanium cap from at least one of the at least two vertical fins in the first subset, and at least one of the at least two vertical fins in the second subset.

Abstract: Subject matter disclosed herein may relate to devices formed from correlated electron material.

Abstract: The invention discloses a three-dimensional complementary-conducting-strip (CCS) structure. Some two-dimensional mesh metal layers are stacked vertically and connected mutually via numerous vias to form a three-dimensional network structure, and one or more signal lines with three-dimensional trace style(s) are positioned inside and separated away the three-dimensional network structure. Moreover, each two-dimensional mesh metal layer is a planar metal layer with one or more empty areas. The three-dimensional network structure is grounded, the signal lines(s) is electrically connected to the device(s) and/or terminal(s) respectively, and the dielectric material(s) is used to electrically insulate the signal line(s) from the three-dimensional network structure.

Abstract: Embodiments include devices and methods for detecting particles, monitoring etch or deposition rates, or controlling an operation of a wafer fabrication process. In an embodiment, one or more micro sensors are mounted on wafer processing equipment, and are capable of measuring material deposition and removal rates in real-time. The micro sensors are selectively exposed such that a sensing layer of a micro sensor is protected by a mask layer during active operation of another micro sensor, and the protective mask layer may be removed to expose the sensing layer when the other micro sensor reaches an end-of-life. Other embodiments are also described and claimed.

Abstract: An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.

Abstract: An IC package is configured to receive a voltage regulator and a load. The IC package includes a plurality of buildup layers disposed on a plurality of core layers. The buildup layers have a top side that includes first and second surface features for receiving the voltage regulator and the load, respectively. First and second pluralities of vias connect the first and second surface features, respectively, to a buildup conductor layer and a core conductor layer. The buildup conductor layer includes a substantially solid or continuous conductor plane extending across and connected to the first and second pluralities of vias. The buildup conductor layer defines a gap between the first and second pluralities of vias, the gap partially separating a portion of the conductor plane connected to the first plurality of vias from a portion connected to the second plurality of vias.

Abstract: A semiconductor device package ready for assembly includes: a semiconductor substrate; a first under-bump-metallurgy (UBM) layer disposed on the semiconductor substrate; a first conductive pillar disposed on the first UBM layer; and a second conductive pillar disposed on the first conductive pillar. A material of the first conductive pillar is different from a material of the second conductive pillar, and the material of the second conductive pillar includes an antioxidant.

Abstract: A semiconductor memory device includes a conductive layer; electrode layers stacked on the conductive layer; an insulating body extending through the electrode layers; and a semiconductor layer positioned between the insulating body and the electrode layers. The plurality of electrode layers include a first electrode layer, a second electrode layer provided between the conductive layer and the first electrode layer, and a third electrode layer provided between the conductive layer and the second electrode layer, and the semiconductor layer has a first layer thickness between the insulating body and the first electrode layer, a second layer thickness between the insulating body and the second electrode layer and a third layer thickness between the insulating body and the third electrode layer. The first layer thickness is thinner than the second layer thickness, and the second layer thickness is thinner than the third layer thickness.

Abstract: A metal protected fan-out cavity enables assembly of a package-on-package (PoP) integrated circuit while reducing PoP solder spacing and overall z-height. A horizontal fan-out conductor provides a contact between a die contact and a lower package via. A metal protection layer may be used during manufacture to protect the fan-out conductor, such as providing a laser stop during laser skiving. The metal protection layer materials and an etching solution may be selected to allow for subsequent removal via etching while leaving the fan-out conductor intact. The metal protection layer and fan-out conductor materials may also be selected to reduce or eliminate formation of an intermetallic compound (IMC) between the metal protection layer and the fan-out conductor.

Abstract: In the examples provided herein, a device is described that has a stack of structure layers including a first structure layer and a second structure layer that are different materials, where the first structure layer is positioned higher in the stack than the second structure layer. The device also has a first sidewall spacer deposited conformally and circumferentially around an upper portion of the stack that includes the first structure layer. Further, the device has a second sidewall spacer deposited conformally and circumferentially around the first sidewall spacer and an additional portion of the stack that includes the second structure layer, where a height of the first sidewall spacer along the stack is different from a height of the second sidewall spacer.