Abstract: In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate, source/drain epitaxial layers disposed between two adjacent gate structures, and an etching-stop layer (ESL) covering the source/drain epitaxial layers. An opening is formed in the ILD layer by etching. A dielectric filling layer is formed in the opening. By using wet etching, the ILD layer disposed above the source/drain epitaxial layers is removed. The ESL disposed on the source/drain epitaxial layers is removed, thereby at least partially exposing the source/drain epitaxial layers. A conductive material is formed over the exposed source/drain epitaxial layers.

Abstract: Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. By way of example, a metal-gate line is formed over the first and second gate regions. In some embodiments, the metal-gate line extends from the first fin to the second fin, and the metal-gate line includes a sacrificial metal portion. In various examples, a line-cut process is performed to separate the metal-gate line into a first metal gate line and a second gate line. In some embodiments, the sacrificial metal portion prevents lateral etching of a dielectric layer during the line-cut process.

Abstract: A negative differential resistance (NDR) device for non-volatile memory cells in crossbar arrays is provided. Each non-volatile memory cell is situated at a crosspoint of the array. Each non-volatile memory cell comprises a switching layer in series with an NDR material containing fast diffusive atoms that are electrochemically inactive. The switching layer is positioned between two elec-trodes.

Abstract: The present technology relates to an imaging device, a manufacturing device, and a manufacturing method capable of preventing a substance such as hydrogen from entering and preventing change in performance. The imaging device includes an organic photoelectric conversion film, an upper electrode provided in an upper portion of the organic photoelectric conversion film, a lower electrode provided in a lower portion of the organic photoelectric conversion film, and a metal thin film provided between the organic photoelectric conversion film and the upper electrode or between the organic photoelectric conversion film and the lower electrode. The metal thin film is provided between the organic photoelectric conversion film and the upper electrode. The upper electrode is formed of an oxide semiconductor, a metal oxide, and the metal thin film. The present technology can be applied to a vertical spectral imaging device.

Abstract: A display apparatus is provided. The display apparatus includes a substrate, a transistor, a metal layer, and a light-emitting diode. The transistor is disposed on the substrate. The metal layer is disposed on the transistor and electrically connected to the transistor, wherein a first distance is between the upper surface of the metal layer and the substrate in a direction perpendicular to the substrate. The light-emitting diode is disposed on the metal layer, wherein the light-emitting diode includes a light-emitting diode body and an electrode, the light-emitting diode body is electrically connected to the metal layer via the electrode, the light-emitting diode body has a first surface and a second surface opposite to the first surface, the first surface and the second surface are parallel to the substrate, and in the direction above, a second distance is between the first surface and the second surface, wherein the ratio of the second distance to the first distance is greater than or equal to 0.

Abstract: A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate. Individual of the capacitor electrode lines are common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed. A capacitor insulator is formed over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines. An elevationally-extending conductive line is formed over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines. The conductive line is cut laterally through to form spaced individual other of the two capacitor electrodes of the individual capacitors. Other methods are disclosed, including structures independent of method of manufacture.

Abstract: Embodiments of a light-emitting element and a light-emitting element array comprise: a light-emitting structure which includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; first and second electrodes which are disposed respectively on the first and second conductive type semiconductor layers; and an insulation layer which is disposed on the light-emitting structure exposed between the first electrode and the second electrode, wherein the second electrode comprises a light-emitting element including: a first part which overlaps with the second conductive type semiconductor layer in the thickness direction of the light-emitting structure; and a second part which extends from the first part and does not overlap with the second conductive type semiconductor layer in the thickness direction, thereby being capable of improving the productivity of a light-emitting element manufacturing process while minimizing the light leakage phenomenon between the

Abstract: A method for fabricating a ferroelectric tunnel junction, comprising growing a hafnium zirconium oxide film barrier layer by sputtering in the presence of oxygen at a temperature of at most 425° C., on a conductive material as a bottom electrode, and depositing a conductive material as a top electrode.

Abstract: An electrical device may include a substrate; a first doped region of the substrate having a p doping type; a second doped region adjacent to the first doped region of the substrate having an n doping type, wherein an interface between the first and second doped regions forms a p-n junction; and a circuit element placed in spaced relation to the p-n junction, the circuit element configured to produce an electric field that interacts with the p-n junction to change a reverse breakdown voltage of the p-n junction. Applicants for the electrical device include ESD protection circuits.

Abstract: An IC chip includes a logic circuit cells array and a static random access memory (SRAM) cells array. The logic circuit cells array includes a plurality of logic circuit cells abutted to one another in a first direction. The logic circuit cells array includes one or more continuous first fin lines that each extends across at least three of the abutted logic circuit cells in the first direction. The static random access memory (SRAM) cells array includes a plurality of SRAM cells abutted to one another in the first direction. The SRAM cells array includes discontinuous second fin lines.

Abstract: A light-emitting device includes: a rectangular shape with a 1st side, a 2nd side opposite to the 1st side, and a 3rd side connecting the 1st and the 2nd sides; a first electrode pad formed adjacent to the 3rd side; a second electrode pad formed adjacent to the 2nd side; a first extension electrode, extending from the first electrode pad in a direction away from the 3rd side and bended toward the 2nd side; and a second extension electrode, including a first and a second branches respectively extending from the second electrode pad; wherein a distance between the first electrode pad and the 3rd side is smaller than a distance between the second electrode pad and the 3rd side; wherein an end portion of the first branch includes a first arc bending to the 3rd side and a minimum distance between the first branch and the 1st side is smaller than a minimum distance between the second branch and the 1st side.

Abstract: Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.

Abstract: A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material. An interfacial layer is formed on the channel structure. A gate stack including a gate electrode layer and a gate dielectric layer is formed over the interfacial layer. Source and drain contacts are formed over openings in the interfacial layer. The source and drain contacts have a side contact with the interfacial layer and a side contact and a surface contact with the channel structure.

Abstract: A semiconductor structure includes a substrate and a patterned magnetic feature disposed over a top surface of the substrate. The patterned magnetic feature is a magnetic material, and has undercut sidewalls providing a self-stop for electro-etching of the magnetic material. The semiconductor structure may form a closed-yoke inductor or a solenoid inductor.

Abstract: A power electronics module and a method of manufacturing a power electronics module and a base plate. The power electronics module comprising at least one power electronics component, wherein the power electronics module comprises a base plate for transferring heat generated by the at least one power electronics component to a cooling device, the base plate comprising a layered structure having a first copper layer, a second copper layer and a carbon based layer between the first and second copper layers.

Abstract: A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL extends from the active area to the trench isolation region. A contact plug is disposed above the trench isolation region and is electrically connected to the gate or the doping region through the RCL.

Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, precursors, in a gaseous form, may be utilized in a chamber to build a film of correlated electron materials comprising various impedance characteristics.

Abstract: Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided.

Abstract: An anti-electrostatic device used in an array substrate of a liquid crystal display and a method for manufacturing the same, and a substrate are disclosed. The method includes steps of: forming a first insulation layer on a first conductive layer; forming a pattern on the first insulation layer; forming an etching barrier layer on the pattern; forming a first via hole and a second via hole extending through the etching barrier layer, and forming a fifth via hole extending through the etching barrier layer and the first insulation layer; forming a second conductive layer on the etching barrier layer, wherein a first portion and a second portion of the second conductive layer are respectively electrically connected to the pattern via the first via hole and the second via hole, and one of them is electrically connected to the first conductive layer via a fifth via hole.

Abstract: In various approaches room-temperature gamma detector longevity may be improved by selectively removing, or selectively incorporating, alternate halogen component(s) from select surfaces of the detector. According to one embodiment, a method of improving operational longevity of a thallium bromide (TlBr)-based detector includes: selectively treating one or more surfaces of the TlBr-based detector to produce a surface substantially comprising pure TlBr. Similar techniques may be employed to restore a degraded or failed detector. According to another embodiment, a method of forming a TlBr-based detector exhibiting improved operational longevity includes: selectively treating one or more surfaces of the TlBr-based detector to replace Br therein with one or more alternate halogen components while also substantially avoiding replacing some or all of the Br in other surfaces of the TlBr-based detector with the one or more alternate halogen components.