Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Abstract: A first dynamic flash memory cell formed on a first Si pillar 25a including an N+ layer 21a, a P layer 22a, and an N+ layer 21b, and a second dynamic flash memory cell formed on a second Si pillar 25b including a P layer 22b and an N+ layer 21c, the first dynamic flash memory cell and the second dynamic flash memory cell sharing the N+ layer 21b that is connected to a first bit line BL1, are stacked on top of one another on a P-layer substrate 20 to form a dynamic flash memory. In plan view, a first plate line PL1, a first word line WL1, a second word line WL2, and a second plate line PL2 extend in the same direction and are formed to be perpendicular to a direction in which the first bit line BL1 extends.

Abstract: An endoscope including an elongated shaft. The elongated shaft including: an inner shaft tube in which an optical system is received; an outer shaft assembly including an outer shaft tube and a tubular support body proximally abutting the outer shaft tube; at least one bundle of optical fibers disposed between the inner shaft tube and the outer shaft tube; and an electrical connector arranged between the inner shaft tube and the support body. Where the support body includes at least a first web and a second web each extending radially between an inner surface of the support body and an outer surface of the inner shaft tube, the first web and the second web also extending in a longitudinal direction of the shaft such that an annular space between the inner shaft tube and the support body is divided into at least two segments.

Abstract: There are provided a method for testing failure of a memory, an apparatus for testing failure of a memory, a computer-readable storage medium, and an electronic device. The method for testing failure of a memory includes: writing preset storage data into a storage array of the memory (S310); raising a bit line voltage, and controlling a part of word lines of the storage array to enter a test mode (S320); exiting the test mode after waiting for preset time (S330); turning off sense amplifiers corresponding to a preset part of bit lines, and reading data from a remaining part of the bit lines (S340); comparing the data read from the remaining part of the bit lines with the preset storage data to obtain a comparison result (S350); and determining a failure state of the memory according to the comparison result (S360).

Abstract: Systems, devices, and methods for controlling cooperative surgical instruments are provided. Various aspects of the present disclosure provide for coordinated operation of surgical instruments accessing a common body cavity of a patient from different approaches to achieve a common surgical purpose. For example, various methods, devices, and systems disclosed herein can enable the coordinated treatment of surgical tissue by disparate minimally invasive surgical systems that approach the tissue from varying anatomical spaces and operate in concert with one another to effect a desired surgical treatment.

Abstract: Technology is disclosed herein for a memory system that balances peak Icc with programming speed. A memory system applies voltages to respective word lines during a verify operation that balances peak Icc with programming speed. The voltages for which the ramp rate is controlled include a read pass voltage applied to unselected word lines and a spike voltage applied to the selected word line at the beginning of the verify. The ramp rate of the voltages is slow enough to keep the peak Icc during verify to a target peak Icc regardless of which word line is selected for verify. However, the ramp rate of the voltages to the word lines during verify is fast enough to make use of the target peak Icc in order achieve faster programming. Therefore, the impact on programming time is minimized while staying within the allowed peak Icc.

Abstract: A retractable syringe device includes: a handle including a hollow body for receiving a syringe through an opening of the handle, the hollow body including a syringe actuator that moves the syringe between a distal position and a proximal position; and an instrument distally extending from the handle, the instrument including a channel extending through the instrument, the channel configured to receive a needle coupled to the syringe. When the syringe is in the distal position, a distal end of the needle distally extends from the instrument, and when the syringe is in the proximal position, the distal end of the needle is retracted into the channel. The handle of the device can include a fixed or removable structure for removably coupling to a proximal end of a shaft of an endoscope.

Abstract: A system for providing on-demand functionality during a medical procedure includes an instrument, an accessory, and a mounting device attached to one or more of the instrument and the accessory. The instrument includes an instrument body and an end effector. The end effector providing a first functionality. The accessory providing a second functionality. The mounting device removably couples the accessory to the instrument to augment the first functionality with the second functionality. In one example, the end effector includes jaws to provide a surgical functionality, and the first accessory includes a camera to provide a complementary monitoring functionality. In another example, the mounting device includes a mechanical mechanism and/or a magnetic mechanism for removably coupling the accessory to the instrument.

Abstract: A PUF apparatus comprises: a PUF cell array in which a plurality of PUF cells are arranged each including a FeFET pair whose gates are commonly connected to a corresponding word line among a plurality of word lines, and whose drains and sources are connected to a corresponding bit line pair and a corresponding source line pair among a plurality of bit line pairs and a plurality of source line pairs running in a direction crossing the plurality of word lines; and a read-write-back block which is activated according to a read enable signal, and senses and amplifies a voltage difference occurring in a corresponding bit line pair among the plurality of bit line pairs according to the difference in driving strength due to a deviation in a manufacturing process of the FeFET pair in the PUF cell selected by a selected word line among the plurality of word lines.

Abstract: Fluorescence videostroboscopy imaging is described. A system includes an emitter for emitting pulses of electromagnetic radiation and an image sensor comprising a pixel array for sensing reflected electromagnetic radiation. The system includes a controller configured to cause the emitter to emit the pulses of electromagnetic radiation at a strobing frequency determined based on a vibration frequency of vocal cords of a user. The system is such that at least a portion of the pulses of electromagnetic radiation emitted by the emitter comprises electromagnetic radiation having a wavelength from about 770 nm to about 790 nm and from about 795 nm to about 815 nm.

Abstract: A tip part assembly for an endoscope, a method for assembling the tip part assembly, and an endoscope including the tip part assembly. The tip part assembly includes a flexible printed circuit having connection points, a camera module including a connection surface comprising connection points arranged in a first connection point pattern for electrical communication with the connection points of the flexible printed circuit, and a converter circuit board including a first surface including connection points arranged substantially in the first connection point pattern and a second surface including connection points arranged in a second connection point pattern being different than the first connection point pattern, wherein the first surface connection points are connected to the connection surface connection points, and wherein the second surface connection points are connected to the connection points of the flexible printed circuit.

Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line.

Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the

Abstract: A memory apparatus includes an address decoding circuit configured to output a test redundancy address based on an address that is transmitted from a memory controller; and a redundancy address check circuit configured to determine whether the test redundancy address is replacing a failed address, in order to perform an ECC test operation by using the test redundancy address.

Abstract: A memory controller, to control a semiconductor memory device, includes an access pattern profiler, a row hammer prediction neural network, and a memory interface. The access pattern profiler generates an access pattern profile based on a row access pattern on a portion of memory cell rows of the semiconductor memory device during a reference time interval posterior to a refresh interval during which the memory cell rows are refreshed. The row hammer prediction neural network predicts a probability of occurrence based on the access pattern profile. In response to the probability being equal to or greater than a reference value, the row hammer prediction neural network generates a hammer address, an alert signal indicating that the row hammer occurs, and an outcast row list. The memory interface transmits the hammer address, the outcast row list, and the alert signal to the semiconductor memory device.

Abstract: A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.

Abstract: An integrated circuit die includes memory sectors, each memory sector including a memory array. The die includes a voltage regulator with a first transistor driven by an output voltage to thereby generate a gate voltage, the output voltage being generated based upon a difference between a constant current and a leakage current. A selection circuit selectively couples the gate voltage to a selected one of the plurality of memory sectors. A leakage detector circuit drives a second transistor with the output voltage to thereby generate a copy voltage based upon a difference between a variable current and a replica of the constant current, increases the variable current in response to the copy voltage being greater than the gate voltage, and asserts a leakage detection signal in response to the copy voltage being less than the gate voltage, the leakage detection signal indicating excess leakage within the memory array.

Abstract: A steerable catheter driven by a robotic controller comprises: a catheter body having a tool channel extending from a proximal to a distal end; and a positioning mechanism configured to be coupled with an imaging device and to be slidably inserted into and/or withdrawn from the catheter body through the tool channel. The positioning mechanism and/or the catheter body include an anti-twist feature configured to interlock the catheter body to the imaging device at the distal end of the catheter body so as to prevent rotation of the imaging device within the tool channel. Anti-twist features include bumps or recesses formed in the tool channel inner surface to be interlocked with one or more features formed on the positioning mechanism outer surface. Position and/or orientation of the imaging device remain substantially unchanged with respect to the tool channel when the catheter body is steered by an actuating force.

Abstract: A medical system including: a trocar configured to provide an artificial access to a body cavity of a patient; a medical instrument configured to be inserted through the trocar and into the body cavity of the patient for performing a medical function in the body cavity of the patient; and a controller configured to: determine whether the medical instrument is inserted into the trocar; and enable the performing of the medical function by the medical instrument only if the medical instrument is determined to be inserted into the trocar.

Abstract: The present invention relates to a testing method, a testing system, and a testing apparatus for a semiconductor chip. The method includes: acquiring a target chip; obtaining an abnormal chip after a test of read and write functions is performed separately on a preset number of memory cells in an edge region of the target chip; recording location information of individual memory cells with abnormal read and write functions on the abnormal chip; judging whether an abnormality of read and write functions of the abnormal chip is a block abnormality based on the location information; wherein the abnormal chip refers to the target chip including the memory cell with abnormal read and write functions.