Patents Examined by Tuan T. Nguyen
  • Patent number: 10453847
    Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 22, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 10448814
    Abstract: An insufflation and irrigation valve for an endoscope including a valve housing with a substantially cylindrical bore closed at one end by a bottom into which a gas inlet and outlet, and an irrigation inlet and outlet open, an outer plunger which is movable in the bore between an open position, in which the irrigation outlet is connected to the inlet, and a closed position, and an inner plunger movable in a longitudinal bore of the outer plunger, open toward the bottom, for connecting the gas outlet to the gas inlet in a position near the bottom and for separating the gas outlet from the gas inlet in a position remote from the bottom, wherein the gas inlet opens into the bore of the valve housing at a location nearer the bottom than the gas outlet.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: October 22, 2019
    Assignee: Karl Storz SE & Co. KG
    Inventors: Clemens Rebholz, Peter Tobien
  • Patent number: 10446196
    Abstract: A dual-power-domain SRAM is disclosed in which the dual power domains may be powered up or down in whatever order is desired. For example, a (CX) power domain may be powered up first, followed by a memory (MX) power domain. Conversely, the MX power domain may be powered up prior to the CX domain.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: October 15, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Mukund Narasimhan, Sharad Kumar Gupta, Adithya Bhaskaran, Sei Seung Yoon
  • Patent number: 10446203
    Abstract: Aspects of the present disclosure include a memory sub-system configured to reduce latency and power consumption during a read-write cycle. The memory system comprises a first memory component and a processing device operatively coupled to the first memory component. The processing device is configured to receive a request to write a first sequence of data bits from a first data block of a second memory component to memory media of the first memory component. In response to receiving the request, the processing device reads a second sequence of data bits from a second data block stored in the memory media of the first memory component, and compares the first sequence of data bits with the second sequence of data bits.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Jeffrey Frederiksen
  • Patent number: 10431281
    Abstract: Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Richard E. Fackenthal, Daniele Vimercati, Jahanshir Javanifard
  • Patent number: 10418086
    Abstract: A volatile memory storage apparatus including a memory array, a refresh circuit and a pre-programmed circuit is provided. The memory array includes a plurality of memory banks. The refresh circuit is coupled to the memory array. The refresh circuit is configured to refresh the memory banks according to different refresh frequencies. The pre-programmed circuit is coupled to the refresh circuit. The pre-programmed circuit is configured to store the refresh frequencies. In addition, a refresh method of a volatile memory storage apparatus is also provided.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 17, 2019
    Assignee: Windbond Electronics Corp.
    Inventor: Chih-Jing Lai
  • Patent number: 10410737
    Abstract: Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. The recovery voltage may have a greater amplitude than the access voltage and may include multiple voltage pulses or a constant voltage. The recovery operation may be performed in the background as the memory array operates, or it may be performed when a host device is not actively using the memory array. The recovery operations may be performed periodically or may include discrete series of pulses distributed among several instances.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Marcello Mariani, Giorgio Servalli, Andrea Locatelli
  • Patent number: 10403358
    Abstract: According to one embodiment, a semiconductor memory device includes a nonvolatile memory comprising a plurality of memory cells, and a controller configured to perform, a preliminary write process of writing reverse data into a first memory cell, and a main write process of writing correct data in the first memory cell, when the first memory cell is in a weak bit state, wherein a condition of the preliminary write process is different from a condition of the main write process.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: September 3, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Shimizu
  • Patent number: 10403361
    Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: September 3, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10403341
    Abstract: A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: September 3, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Nobuhiro Tsuji, Hiroki Ohkouchi, Shota Note, Masashi Nakata, Yohei Yasuda
  • Patent number: 10395716
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. In some examples, multi-level accessing, sensing, and other operations for ferroelectric memory may be based on sensing multiple charges, including a first charge associated with a dielectric of the memory cell and a second charge associated with a polarization of the memory cell. In some cases, multi-level accessing, sensing, and other operations may be based on transferring a first charge associated with a dielectric of the memory cell to a sense amplifier, isolating the sense amplifier, activating the sense amplifier, transferring a second charge associated with a polarization of the memory cell to the sense amplifier, and activating the sense amplifier a second time.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Christopher John Kawamura
  • Patent number: 10395700
    Abstract: Embodiments of the present disclosure provide a circuit structure including: first PMOS and second PMOS each including a gate, source, and drain; wherein sources of first and second PMOS are coupled to first voltage source, gate of first PMOS is cross coupled to drain of second PMOS, gate of second PMOS is cross coupled to drain of first PMOS, drain of the first PMOS is coupled to first bit-line node, and wherein drain of second PMOS is coupled to second bit-line node; write bit-switch having first NMOS coupled to first bit-line node and second NMOS coupled to second bit-line node, wherein first and second NMOS of write bit-switch are respectively coupled to a pair of data nodes each receiving one of a pair of data inputs; and write driver, having a pair of transistor stacks each coupled to between one of the pair of data nodes and ground.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: August 27, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Venkatraghavan Bringivijayaraghavan, Sreenivasa Chaitanya Kumar Vavilla
  • Patent number: 10388378
    Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: August 20, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10381058
    Abstract: An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: August 13, 2019
    Assignee: SK hynix Inc.
    Inventor: Byeong Cheol Lee
  • Patent number: 10381057
    Abstract: An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: August 13, 2019
    Assignee: SK hynix Inc.
    Inventor: Byeong Cheol Lee
  • Patent number: 10381071
    Abstract: A multi-bit computing circuit for computing-in-memory applications is controlled by an input port and includes a memory cell array and a capacitor sharing unit. The memory cell array includes a plurality of memory cells connected to the input port. The memory cells store a weight which is formed in two's complement. The capacitor sharing unit includes a plurality of switches, a plurality of capacitors and a sense amplifier. The switches are electrically connected to the memory cells, respectively. The capacitors are electrically connected to the switches, respectively. The sense amplifier is electrically connected to the capacitors and generates a total operational value. The capacitors are located among the switches and the sense amplifier, and the switches are switched to enable the total operational value to be equal to the input value multiplied by the weight. The present disclosure utilizes 8T SRAM cells without an extra DAC structure.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 13, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Xin Si, Meng-Fan Chang
  • Patent number: 10373660
    Abstract: Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks responsive to complementary input clocks. The clock circuit is further configured to be in a first mode or second mode controlled by the control signal and configured to provide the multiphase clocks having greater duty cycle distortion in a first mode than in a second mode.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim, John D. Porter
  • Patent number: 10366768
    Abstract: Disclosed are a memory device, including: a memory block including a plurality of cell strings; a peripheral circuit configured to set voltages for a program operation of selected memory cells in the cell strings, and program the selected memory cells by using the set voltages; and a control circuit configured to control the peripheral circuit so that the selected memory cells are programmed in response to a program command, and increase a channel voltage of non-selected cell strings including non-selected memory cells while the selected memory cells are programmed, and an operating method thereof.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: July 30, 2019
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10366023
    Abstract: An operation method performed at a nonvolatile memory device may include receiving a program command and an address from an external device through a data signal (DQ), receiving a specific pattern from the external device through the data signal and a data strobe signal (DQS) synchronized with the data signal in a pattern period, receiving user data from the external device through the data signal and the data strobe signal in a data period, and selectively performing a program operation on the user data or a recovery operation based on a determination of whether the specific pattern matches with a particular pattern. A rising edge or a falling edge of the data strobe signal may be aligned with a left edge or a right edge of a window of the data signal in the pattern period.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: July 30, 2019
    Inventors: YoungWook Kim, Hyung-jin Kim, Soong-Man Shin, Keun-Hwan Lee
  • Patent number: 10366762
    Abstract: A semiconductor memory device includes a cell string, a common source line controller, and a page buffer. The cell string includes a plurality of memory cells coupled in series between a common source line and a bit line. In a read operation, the common source line controller provides a channel current to the cell string through the common source line. The page buffer senses data stored in a selected memory cell among the plurality of memory cells by sensing a current of the bit line when the channel current is provided. The common source line controller precharges the bit line by providing the channel current to the cell string through the common source line. After the bit line is precharged, the page buffer senses the data stored in the selected memory cell by transmitting a voltage of the bit line to a sensing node.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: July 30, 2019
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee