Abstract: A memory controller, to control a semiconductor memory device, includes an access pattern profiler, a row hammer prediction neural network, and a memory interface. The access pattern profiler generates an access pattern profile based on a row access pattern on a portion of memory cell rows of the semiconductor memory device during a reference time interval posterior to a refresh interval during which the memory cell rows are refreshed. The row hammer prediction neural network predicts a probability of occurrence based on the access pattern profile. In response to the probability being equal to or greater than a reference value, the row hammer prediction neural network generates a hammer address, an alert signal indicating that the row hammer occurs, and an outcast row list. The memory interface transmits the hammer address, the outcast row list, and the alert signal to the semiconductor memory device.

Abstract: An integrated circuit die includes memory sectors, each memory sector including a memory array. The die includes a voltage regulator with a first transistor driven by an output voltage to thereby generate a gate voltage, the output voltage being generated based upon a difference between a constant current and a leakage current. A selection circuit selectively couples the gate voltage to a selected one of the plurality of memory sectors. A leakage detector circuit drives a second transistor with the output voltage to thereby generate a copy voltage based upon a difference between a variable current and a replica of the constant current, increases the variable current in response to the copy voltage being greater than the gate voltage, and asserts a leakage detection signal in response to the copy voltage being less than the gate voltage, the leakage detection signal indicating excess leakage within the memory array.

Abstract: A steerable catheter driven by a robotic controller comprises: a catheter body having a tool channel extending from a proximal to a distal end; and a positioning mechanism configured to be coupled with an imaging device and to be slidably inserted into and/or withdrawn from the catheter body through the tool channel. The positioning mechanism and/or the catheter body include an anti-twist feature configured to interlock the catheter body to the imaging device at the distal end of the catheter body so as to prevent rotation of the imaging device within the tool channel. Anti-twist features include bumps or recesses formed in the tool channel inner surface to be interlocked with one or more features formed on the positioning mechanism outer surface. Position and/or orientation of the imaging device remain substantially unchanged with respect to the tool channel when the catheter body is steered by an actuating force.

Abstract: A register management system is coupled to a register. The register management system receives an address and functional data for a write operation to be performed on the register. The functional data includes write bits and mask bits associated with the write bits. One or more mask bits having a first logic state indicate that associated one or more write bits are to be written to the register, respectively. Based on the address, the register management system selects a first half of the register or a second half of the register to perform the write operation. Further, the register management system writes the one or more write bits associated with the one or more mask bits having the first logic state to one or more storage elements of the first half of the register or the second half of the register, respectively.

Abstract: The present invention relates to a testing method, a testing system, and a testing apparatus for a semiconductor chip. The method includes: acquiring a target chip; obtaining an abnormal chip after a test of read and write functions is performed separately on a preset number of memory cells in an edge region of the target chip; recording location information of individual memory cells with abnormal read and write functions on the abnormal chip; judging whether an abnormality of read and write functions of the abnormal chip is a block abnormality based on the location information; wherein the abnormal chip refers to the target chip including the memory cell with abnormal read and write functions.

Abstract: A medical system including: a trocar configured to provide an artificial access to a body cavity of a patient; a medical instrument configured to be inserted through the trocar and into the body cavity of the patient for performing a medical function in the body cavity of the patient; and a controller configured to: determine whether the medical instrument is inserted into the trocar; and enable the performing of the medical function by the medical instrument only if the medical instrument is determined to be inserted into the trocar.

Abstract: Methods, systems, and devices for read command fault detection in a memory system are described. For example, a memory device may be configured to set a field of a register with a first value, corresponding to a state where a read command has not been decoded. If the memory device receives and decodes a read command from a host device, the memory device may set the field with a second value. The memory device indicate a value of the field of the register to the host device, which may be used to evaluate whether to process information interpreted over an interface between the host device and the memory device. For example, if the host device receives an indication of the second value, the host device may proceed with processing and, if the host device receives an indication of the first value, the host device may refrain from processing.

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.

Abstract: A monitor device and a method of using the monitor device in a medical visualisation system including a visualisation device having an image sensor configured to generate image data indicative of a view, the monitor device configured to operate in a first interface orientation mode and a second interface orientation mode, wherein in the first interface orientation mode, a second portion is between a fourth housing side and a first portion, and wherein in the second interface orientation mode, the second portion is between a third housing side and the first portion.

Abstract: A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region.

Abstract: Disclosed herein are various robotic surgical systems having various robotic devices. Further, disclosed herein are removable coupleable connection ports, each of which can be coupled to a robotic device and a camera assembly that is disposed into and through the robotic device. Also disclosed herein are removable connection ports having at least one of a elongate device body coupling mechanism, a camera assembly coupling mechanism, and/or a presence detection mechanism. Further discussed herein is a camera assembly with at least one actuation mechanism for actuating movement of the steerable distal tip thereof.

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Abstract: Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.

Abstract: A method and a device for testing a memory chip are provided. The method includes: writing test data into memory cells of a memory chip to-be-tested; reading stored data from the memory cells; and generating a test result of the memory chip to-be-tested according to the test data and the stored data; a word line turn-on voltage tested in the memory chip to-be-tested being greater than a standard bit line and word line turn-on voltage of the memory chip to-be-tested, and/or a sense amplification time tested in the memory chip to-be-tested being greater than a standard sense amplification time of the memory chip to-be-tested.

Abstract: An endoscope including: a shaft; a main body arranged at a proximal end of the shaft; an eyepiece arranged at a proximal end of the main body; an eyepiece system tube, in which the eyepiece is arranged; an eyepiece cone arranged at a proximal end of the eyepiece, wherein the eyepiece cone comprises at least two parts; and an electronic component arranged between the at least two parts of the eyepiece cone; wherein the electronic component is connected to an electronic circuit arranged inside the endoscope and outside the eyepiece system tube.

Abstract: An observation instrument includes an instrument shaft having a distal end and a proximal end, and an optical arrangement extending at least sectionally through the instrument shaft. The optical arrangement includes at least one optical component that is accommodated in a support shaft. The support shaft is arranged in the instrument shaft in an at least sectionally axially displaceable manner and is preloaded distally.

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.

Abstract: An endoscope system includes an insertion portion receiving a first force from an enteric canal and applying a second force, which is a reaction, to the enteric canal, a detection device detecting a position of the insertion portion, and a processor. The processor calculates a position of a point of application, a direction, and a magnitude of the first force, performs an arithmetic operation of a shape/position of the insertion portion based on an output from the detection device, determines a reaction position at which the second force is received, based on position information of the insertion portion and on position information of the point of application of the first force, sets two fixed points where the enteric canal is fixed, and calculates information of a third force and a fourth force directed toward the two fixed points from the reaction position with respect to the second force.

Abstract: An ECC decoder includes: a memory comprising a memory region; a first converter configured to transmit a hard bit, received from a channel, to the memory to store the hard bit in a first area of the memory region; a second converter configured to receive the hard bit read from the first area and output a reliability value corresponding to the hard bit, whenever a hard decoding operation on the hard bit is iterated; and a variable node configured to perform the hard decoding operation using the reliability value.