Abstract: A medical control device includes: a light source controller configured to modulate pulsed light by changing a crest value of a pulsed current and emit the pulsed light a plurality of times from the light source in one frame; an imaging controller configured to cause an image sensor to sequentially generate a pixel signal at a specific frame rate; and an image processor configured to use a pixel signal obtained by multiplying the pixel signal for specific one frame from each pixel of a specific horizontal line by a ratio of an amount of exposure of specific pulsed light made in the specific one frame to a total exposure amount obtained by adding each exposure amount of all of the pulsed lights exposing the specific horizontal line within the specific one frame including an illumination period of the specific pulsed light.

Abstract: The disclosure relates to a method and system for memory testing to detect memory errors during operation of a memory module. Example embodiments include a method of detecting an error in a memory module (101), the method comprising the sequential steps of: i) receiving (302) a request from a processor executing an application for a read or write operation at a location of the memory module (101) identified by an address; ii) outputting data (304) from, or writing to, the location of the memory module (101); iii) generating (306) by an error detection module (102) a further read request for the location of the memory module (101) identified by the address; iv) receiving (307) at the error detection module (102) an error correction code from the memory module (101) for the location identified by the address; and vi) providing (311) by the error detection module (102) an alert output for the address if the error correction code indicates an error.

Abstract: Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. High voltage circuits used to generate high voltages applied to terminals of the non-volatile memory cells during the precision tuning process are also disclosed. Programming sequences for the application of the voltages to the terminals to minimize the occurrence of disturbances during tuning are also disclosed.

Abstract: A component includes a memory region containing optically active material, a control arrangement configured to provide at least one control signal configured to change optical properties of the optically active material, and a detector configured to detect a change in the optical properties of the optically active material. The detector includes an evaluation input region configured to receive at least one evaluation input signal and an evaluation output region configured to provide an evaluation output signal. The memory region is arranged between the evaluation input region and the evaluation output region, and the control arrangement adjoins the memory region.

Abstract: A controller including: control pins for providing control signals to a nonvolatile memory; a buffer memory configured to store first to third tables; and an error correction code (ECC) circuit configured to correct an error in first data read from the nonvolatile memory according to a first read command, wherein the first table stores first offset information, the second table stores second offset information, and the third table stores third offset information, wherein the third offset information corresponds to a history read level and is determined by the first and second offset information, and when the error of the first data is uncorrectable, an on-chip valley search operation is performed by the nonvolatile memory according to a second read command, detection information of the on-chip valley search operation is received according to a specific command, and the second offset information which corresponds to the detection information is generated.

Abstract: A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.

Abstract: A seeker device for facilitating access to a desired location within an ear, nose, throat or other location in a body may include a proximal shaft, an elastic distal portion, and an atraumatic distal tip. The elastic distal portion has a default shape with at least one curve to facilitate advancement of a distal end of the elastic distal portion through various anatomical passageways, toward the desired location. In some embodiments, the seeker device may be paired with a dilator device, to perform a dilation procedure on an anatomical structure in the ear, nose, throat or other part of the body. In other embodiments, the seeker device may be paired with a flexible endoscope, to facilitate visualization of an anatomical structure or area.

Abstract: According to one or more embodiments, a semiconductor storage device includes a first chip and a second chip. The first chip includes a semiconductor substrate and a plurality of transistors on the semiconductor substrate. The second chip includes a memory cell array and a plurality of first patterns. The memory cell array is connected to the plurality of transistors of the first chip and includes a plurality of memory blocks arranged in a first direction. The plurality of first patterns are spaced from each other in the first direction. Each first pattern represents a different number and is at a position corresponding to one or more of the memory blocks.

Abstract: A data access system includes a flash memory, a first inversion circuit, a block buffer memory, an error checking and correcting circuit, a second inversion circuit, and an application circuit. The first inversion circuit inverts a plurality of pieces of data stored in a block of the flash memory to generate a plurality of pieces of inverted data. The block buffer memory stores the plurality of pieces of inverted data. When the ECC circuit determines that the plurality of pieces of inverted data are correctable, the ECC circuit corrects at least one piece of inverted data stored in the block buffer memory. The second inversion circuit inverts the plurality of pieces of inverted data stored in the block buffer memory to generate a plurality of pieces of recovered data. The application circuit receives the plurality of pieces of recovered data and performs a corresponding operation accordingly.

Abstract: An endoscope system includes at least any one of a processor device that is attachable to and detachable from an endoscope or a light source device that is attachable to and detachable from the endoscope. In a case where the endoscope is mounted on the processor device or the light source device, the processor device or the light source device performs a request sequence in which a request signal, for requesting a start of execution of encoding processing with respect to digital image signals, is transmitted to the endoscope.

Abstract: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Abstract: Methods and apparatuses having an improved write assist scheme are presented. An apparatus includes a power supply node configured to provide power from a power supply to one memory cell to store data; a bitline configured to provide write data to the one memory cell in a write operation; and a discharge circuit configured to selectively discharge the power supply node to the bitline, based on the write data. A method to write into a memory cell with a write assist scheme includes providing power from a power supply to one memory cell via a power supply node, to store data; providing write data to the one memory cell via a bitline in a write operation; and discharging, selectively based on the write data, the power supply node to the bitline.

Abstract: A power down detection circuit that may detect a supply voltage decrease more accurately is provided. The power down detection circuit includes a BGR circuit generating a reference voltage VREF, a resistance division circuit generating a first internal voltage VCC_DIV1 and a second internal voltage VCC_DIV2 based on a supply voltage VCC, a first comparator outputting a reset signal PDDRST when detecting VCC_DIV1<VREF, a second comparator outputting a switching signal SEL when detecting VCC_DIV2<VREF, a charging pump circuit generating a boosted voltage VXX based on the supply voltage VCC, and a switching circuit switching an operating voltage supplied to the BGR circuit to the supply voltage VCC or the boosted voltage VXX based on the switching signal SEL.

Abstract: A memory system includes a plurality of blocks of memory blocks, each including a plurality of memory cells. The method for programming the memory system includes during a program process, performing a first program operation to program a first memory block, waiting for a delay time after the first program operation is completed, after waiting for the delay time, performing an all-level threshold voltage test to determine if threshold voltages of the first memory block are greater than corresponding threshold voltages, and performing a second program operation to program the first memory block according to a result of the all-level threshold voltage test.

Abstract: A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.

Abstract: A system includes a memory array with sub-blocks, each sub-block having groups of memory cells. A processing device, operatively coupled with the memory array, is to perform operations including performing, after a wordline is programmed through the sub-blocks, scanning of the wordline. The scanning includes selecting, to sample first data of the wordline, a first group of the groups of memory cells of a first sub-block of the sub-blocks; selecting, to sample second data of the wordline, a second group of the groups of memory cells of a second sub-block of the sub-blocks; concurrently reading the first data from the first group and the second data from the second group of the groups of memory cells; and performing an error check of the wordline using the first data and the second data.

Abstract: Disclosed herein is an apparatus that includes a first buffer circuit, a plurality of first driver circuits configured to drive the first buffer circuit, and a plurality of first switch circuits configured to supply an operation voltage to the first driver circuits, respectively. The first driver circuits are collectively arranged in a first region in a matrix, and the first switch circuits are collectively arranged in a second region different from the first region.

Abstract: A semiconductor memory device includes a data bus terminal group for outputting read data to an external device or inputting write data from an external device, a first terminal from or into which 1-bit data is output or input, a DBI circuit that executes a Data Bus Inversion (DBI) function, an error detection circuit that detects an internal error, and an information superimposing circuit that superimposes predetermined output information onto the 1-bit data to be output from the first terminal and the read data to be output from the data bus terminal group. The predetermined output information includes first output information indicating whether or not an output bit pattern of the data bus terminal group is inverted, and second output information indicating whether or not an internal error has been detected by the error detection circuit.

Abstract: An error correction circuit includes ECC encoder and an ECC decoder. The ECC encoder generates, based on a first main data obtained by selectively shifting data bits of a main data based on a LSB of a row address, a parity data using an ECC and stores a codeword including the main data and the parity data in a target page. The ECC decoder generates a syndrome based on a second main data obtained by selectively shifting data bits of the main data based on the LSB of the row address, the parity data and a parity check matrix based on the ECC, and corrects a single bit error or corrects two bit errors when the two bit errors occur in adjacent two memory cells based on the syndrome. The mis-corrected bit is generated when the multiple error bits are present in the main data.

Abstract: Methods of testing memory devices are disclosed. A method may include reading from a number of memory addresses of a memory array of the memory device and identifying each memory address of the number of addresses as either a pass or a fail. The method may further include storing, for each identified fail, data associated with the identified fail in a buffer of the memory device. Further, the method may include conveying, to a tester external to the memory device, at least some of the data associated with each identified fail without conveying address data associated with each identified pass to the tester. Devices and systems are also disclosed.