Abstract: Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.

Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.

Abstract: A method for selecting bad columns in a data storage medium is provided. The data storage medium is coupled to a control unit, and the data storage medium includes data blocks, wherein each of the data blocks includes columns. The columns are divided into chunks. The method for selecting bad columns in the data storage medium includes following steps. (a) The control unit calculates a number of bad columns in each of the chunks to sorts the chunks, wherein the bad columns are selected from the columns. (b) The control unit sequentially marks or records the bad columns in each of the chunks with bad column groups, wherein a bad column position and a bad column number in each of the chunks are marked or recorded in each of the bad column groups.

Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.

Abstract: A method includes determining whether a data reliability parameter associated with a set of memory cells is greater than a threshold data reliability parameter and in response to determining that the data reliability parameter is greater than the threshold data reliability parameter, performing an error recovery operation. The method further includes, subsequent to performing the error recovery operation, determining whether the data reliability parameter associated with the set of memory cells is less than the threshold data reliability parameter and in response to determining that the data reliability parameter is less than the threshold data reliability parameter, setting an offset associated with the error recovery operation as a default read voltage for the set of memory cells.

Abstract: A memory system is provided. In the memory system, a memory controller transmits a write enable signal and a data strobe signal to a flash memory device, a command or an address is transmitted at a rising edge or a falling edge of the write enable signal through a data line in a single data rate (SDR) scheme, and input data is transmitted at each of a rising edge and a falling edge of the data strobe signal through the data line in a double data rate (DDR) scheme. The memory controller includes a parity signal generation unit configured to receive the write enable signal transmitted in the DDR scheme and output a parity signal by generating a first parity bit for the input data. The flash memory device includes a bit error detection unit configured to receive the parity signal output from the memory controller, generate a second parity bit for the input data received by the flash memory device, and determine whether a bit error has occurred to the input data by performing a parity check.

Abstract: According to one embodiment, a memory system includes: a memory chip including a first memory block and first word lines, the first memory block including a first memory string which includes first memory cells that are coupled in series, the first word lines being respectively coupled to gates of the first memory cells; a memory controller coupled to an external device, controlling the memory chip, and capable of performing an error checking and correcting process of data. When a write instruction is received from the external device, the memory controller is configured to perform a write operation on a second memory cell which is one of the first memory cells, and to perform a read verify operation including a read process and the ECC process on a third memory cell which is one of the first memory cells.

Abstract: A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.

Abstract: A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.

Abstract: This invention relates to a tip protector for an instrument such as an endoscope or borescope, the instrument comprising an elongate shaft having a distal tip and said tip including an end face. A tip protector device comprises a guard portion including an elongate tubular portion and a cap arranged to extend over the end face of the instrument; first and second connection members extending from the tubular portion and being movable relative to each other between a first, disengaged position in which said tip of the instrument can be inserted into and removed from the guard portion, and a second, gripping position in which the tip protector grips the shaft of the instrument, the first and second connection members being biased in the first position; and complementary engagement features on the first and second connection members configured to retain the first and second connection members in the gripping position.

Abstract: An integrated circuit includes a first array of memory cells, a second array of memory cells, a first pair of complementary data lines, a second pair of complementary data lines, and a third pair of complementary data lines. The first pair of complementary data lines extend along the first array of memory cells, and are coupled to the first array of memory cells. The second pair of complementary data lines extend along the second array of memory cells, and are coupled to the first pair of complementary data lines. The third pair of complementary data lines extend along the second array of memory cells, and are coupled to the second array of memory cells. A number of rows of memory cells in the first array of memory cells is different from a number of rows of memory cells in the second array of memory cells.

Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include local latching circuits each having a retention circuit and a driving circuit. The retention circuit may be configured to provide local storage of broadcasted information for a down-stream circuit. The driving circuit may be configured to connect a first voltage and a second voltage to the retention circuit at different times across the broadcast and the local storage.

Abstract: Technologies for various memory structures for artificial intelligence (AI) applications and methods thereof are described. An XNOR circuit along with a sense amplifier may be combined with an array (or multiple arrays) of memory such as non-volatile memory (NVM) or an NVM, SRAM combination to perform an XNOR operation on the data read from the memory. Various versions may include different connections allowing simplification of circuitry or timing. In some examples, memory array may include programmable resistor/switch device combinations, or multiple columns connected to a single XNOR+SA circuit.

Abstract: A storage device for verifying whether memory cells have been programmed. The storage device may be configured to use a verification technique, that is part of a set of verification techniques, to verify data states of a set of memory cells of a selected word line. The one or more verification techniques may be utilized based on an iteration of the verify operation that is to be performed. The storage device may be further configured to perform, using the verification technique, a next iteration of the program-verify operation to verify whether one or more memory cells have been programmed. Using the verification technique and performing the next-iteration of the program-verify operation are to be repeated until the set of memory cells have been verified.

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a memory cell array having a volatile memory cell and an access control circuit configured to perform a refresh operation on the volatile memory cell, and a second semiconductor chip including a power generator configured to supply a first power supply voltage to the first semiconductor chip. The access control circuit is configured to activate a first enable signal during the refresh operation. The second semiconductor chip is configured to change a capability of the power generator based on the first enable signal.

Abstract: A memory device includes a cell array including cells, an address transition detector outputting a transition detection signal as to whether an address of a write command is changed, and a control logic circuit generating one of word-line-on signals for performing a write operation on the cell array in response to the write command, and terminating the write operation in accordance with the transition detection signal. The word-line-on signals include a long-kept word-line-on signal that stays active before the address is changed and a divided word-line-on signal that is, before the address is changed, divided into sub-word-line-on signals.

Abstract: A memory system performs Error Correcting Code (ECC) decoding on data read from a plurality of target memory cells of a memory device, determines whether to update a read bias used in read operations of the memory device according to results of the ECC decoding, and then may update a value of the read bias based on result data produced by the ECC decoding and the number of data bits corrected by the ECC decoding, thereby optimizing the read bias value according to a change in a threshold voltage distribution of the memory cell, and increasing the likelihood of success of the ECC decoding.

Abstract: A memory system includes a memory module and a memory controller. The memory module includes data chips that store data and are assigned to a first sub-channel that generates a first code word or a second sub-channel that generates a second code word, where the first code word and the second code are used to fill a single cache line. The memory controller, upon detection of a hard-fail data chip among the data chips, copies data from the hard-fail data chip to the ECC chip, releases mapping between the hard-fail data chip and corresponding I/O, and defines new mapping between the ECC chip and the corresponding I/O pins.

Abstract: Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof.

Abstract: The present disclosure relates to an electronic device. A memory device having improved cache program operation performance according to the present technology includes a plurality of memory cells, each programmed in any one of first to n-th program state where n is a natural number greater than, a sensing latch configured to store data sensed from a bit line connected to a selected memory cell among the plurality of memory cells, and a plurality of data latches configured to temporarily store data to be stored in the selected memory cell.