Abstract: Data compression techniques are provided that remove redundancy across the boundary of compression search engines. An illustrative method comprises splitting the data frame into a plurality of sub-chunks; comparing at least two of the plurality of sub-chunks to one another to remove at least one sub-chunk from the plurality of sub-chunks that substantially matches at least one other sub-chunk to generate a remaining plurality of sub-chunks; generating matching sub-chunk information for data reconstruction identifying the at least one removed sub-chunk and the corresponding substantially matched at least one other sub-chunk; grouping the remaining plurality of sub-chunks into sub-units; removing substantially repeated patterns within the sub-units to generate corresponding compressed sub-units; and combining the compressed sub-units with the matching sub-chunk information to generate a compressed data frame.

Abstract: A processing system fills a memory access request for data from a processor core by bypassing a cache when a write congestion condition is detected, and when transferring the data to the cache would cause eviction of a dirty cache line. The cache is bypassed by transferring the requested data to the processor core or to a different cache. Accordingly, the processing system can temporarily bypass the cache storing the dirty cache line when filling a memory access request, thereby avoiding the eviction and write back to main memory of a dirty cache line when a write congestion condition exists.

Abstract: Provided are a computer program product, system, and method for adjusting active cache size based on cache usage. An active cache in at least one memory device caches tracks in a storage during computer system operations. An inactive cache in the at least one memory device is not available to cache tracks in the storage during the computer system operations. During caching operations in the active cache, information is gathered on cache hits to the active cache and cache hits that would occur if the inactive cache was available to cache data during the computer system operations. The gathered information is used to determine whether to configure a portion of the inactive cache as part of the active cache for use during the computer system operations.

Abstract: A technique for determining a data window size allows a set of predicted blocks to be transmitted along with requested blocks. A stream enabled application executing in a virtual execution environment may use the blocks when needed.

Abstract: An integrated data processing core and a data processor are provided on a single integrated circuit and command sequences are forwarded from the data processing core to be executed on the array data processor wherein the command sequences comprise a group of instructions defining an algorithm.

Abstract: Embodiments relate to accessing data in a memory. A method for accessing data in a memory coupled to a processor is provided. The method receives a memory reference instruction for accessing data of a first size at an address in the memory. The method determines an alignment size of the address in the memory. The method accesses the data of the first size in one or more groups of data by accessing each group of data block concurrently. The groups of data have sizes that are multiples of the alignment size.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Abstract: Disclosed herein are a memory device and a method of operating the memory device. The memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell may a plurality of main memory blocks and a plurality of sub-memory blocks included in each of the main memory blocks. The peripheral circuit may perform a program operation on the main memory blocks or the sub-memory blocks, detect an amount of data loaded for the program operation, and output data amount information. The control logic may control the peripheral circuits so that, during the program operation, at least one memory block is selected from the main memory blocks or from the sub-memory blocks according to the data amount information and the program operation is performed on the selected memory block.

Abstract: A data storage system includes a plurality of Data Storage Devices (DSDs) having a total storage capacity available for storing user data among the plurality of DSDs. Each DSD of the plurality of DSDs has a DSD storage capacity that contributes to the total storage capacity of the plurality of DSDs. A strip size is assigned to each DSD of the plurality of DSDs based at least in part on a portion of the total storage capacity that is contributed by the DSD storage capacity of the respective DSD. Data is received for storage in a data stripe across the plurality of DSDs and the data stripe is stored across the plurality of DSDs such that each DSD of the plurality of DSDs stores a different portion of the data stripe having the strip size assigned to the DSD.

Abstract: Embodiments include method, systems and computer program products for operating a resettable write once read many (RWORM) memory. The method includes receiving, by a processor, a request for at least a portion of memory in a computer system to be designated as RWORM memory. The processor further writes data to the RWORM memory. The processor further maintains the RWORM memory in a read-only state after the RWORM memory is written to. The processor further re-designates the RWORM memory to a read/write state in response to encountering a system reset.

Abstract: In general, embodiments of the technology relate to writing data to storage appliances. More specifically, embodiments of the technology are directed to writing data to storage media using a push-based mechanism in which clients provide the data to write to the storage media and then subsequently provide a command to write the data to the storage media.

Abstract: A method includes separating a file into multiple blocks. Each block of the multiple blocks are separated into at least two correlated sub-blocks. Intra-file block organized storage placement on different types of memory devices is determined for the at least two correlated sub-blocks in a file system metadata layout. The intra-file block organized storage placement is based on a predictive column data block placement model that considers multiple attributes of column data blocks.

Abstract: One embodiment provides a method, including: generating, for each of a plurality of storage volumes, an actual used storage capacity model and identifying a potential storage capacity savings using the actual used capacity model, wherein each of the plurality of storage volumes has been identified as a candidate for migration to a thin provisioned volume; generating, for each of the plurality of storage volumes, an input/output profile model and identifying a potential change in performance of an application accessing the storage volume using the input/output profile model; generating, for each of the plurality of storage volumes, a growth profile and identifying a potential change in capacity using the growth profile; and determining, using an optimization algorithm, a subset of the plurality of storage volumes to be migrated to thin provisioned volumes based upon the volume capacity model, the performance model, and the volume growth profile.

Abstract: A memory subsystem manages memory I/O impedance compensation by the memory device monitoring a need for impedance compensation. Instead of a memory controller regularly sending a signal to have the memory device update the impedance compensation when a change is not needed, the memory device can indicate when it is ready to perform an impedance compensation change. The memory controller can send an impedance compensation signal to the memory device in response to a compensation flag set by the memory or in response to determining that a sensor value has changed in excess of a threshold.

Abstract: A storage system includes a first storage apparatus including a first storage portion and a second storage portion, a second storage apparatus including a third storage portion and a fourth storage portion, and a storage management apparatus including a processor configured to control the first storage apparatus in an active state and control the second storage apparatus in a standby state, cause the first storage apparatus to execute first data relocation processing, cause the second storage apparatus to execute second data relocation processing, cause the first storage apparatus to suspend the first data relocation processing and cause the second storage apparatus to continue the second data relocation processing, switch the first storage apparatus from the active state to the standby state and switch the second storage apparatus from the standby state to the active state, and cause the first storage apparatus to resume the first data relocation processing.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Abstract: A data storage device includes a nonvolatile memory device including a main map table, the main map table including a plurality of map segments; and a controller comprising a sub map table including only some of the plurality of map segments of the main map table, the controller is suitable for updating access frequencies for the respective map segments of the main map table; and for determining whether to erase a map segment of the sub map table based on the updated access frequencies for the respective map segments.

Abstract: According to one embodiment, a data processing system includes a plurality of central processing unit (CPU) subsystems, each CPU subsystem having a plurality of CPUs and a plurality of memory controllers, each memory controller corresponding to one of the CPUs, a plurality of memory complexes, each memory complex being associated with one of the CPU subsystems, wherein each memory complex comprises one or more branches, a plurality of memory leaves to store data, wherein each of the branches is coupled to one or more of the memory leaves and to provide access to the data stored in the memory leaves, and a replication interface to automatically replicate data received from one of the CPU subsystems to another one of the memory complexes, wherein the received data is to be stored in one of the memory leaves.

Abstract: A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.

Abstract: A first storage system is configured to participate in a replication process with a second storage system. The first and second storage systems initially operate in an asynchronous replication mode and subsequently transition to a synchronous replication mode. The first and second storage systems concurrently operate in both modes for at least a portion of the transition. While the first and second storage systems are concurrently operating in both modes, the first storage system is configured to detect a given data page that has been subject to one or more write operations in the first storage system since generation of a corresponding set of one or more snapshots for a most recent data transfer cycle of the asynchronous replication mode, to initiate a data transfer request for the given data page, and to update a content-based signature of the given data page. The second storage system determines whether to accept or reject the transfer of the given data page.