Patents Examined by Tuan V. Thai
  • Patent number: 10852968
    Abstract: This application sets forth techniques for managing the allocation of memory storage space in a non-volatile memory to improve the operation of a camera application. A camera application monitors an amount of available memory storage space in the non-volatile memory. Responsive to various triggering events, the camera application compares the amount of available memory storage space to a threshold value. When the amount of available memory storage space is less than the threshold value, the camera application transmits a request to a background service to free additional memory storage space within a temporary data store associated with one or more applications installed on the computing device. The temporary data store provides a location for local data to improve the efficiency of the applications, which can be exploited by the camera application to free up memory to avoid a low-memory condition that could prevent the camera application from performing certain operations.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: December 1, 2020
    Assignee: Apple Inc.
    Inventors: Kazuhisa Yanagihara, Benjamin P. Englert, Cameron S. Birse, Susan M. Grady
  • Patent number: 10852956
    Abstract: Embodiments of the invention provide a novel structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and DRAM burst reordering. Where the external per-bank refresh removes some of the unpredictable nature of PBR commands and DRAM burst reordering provides for efficient utilization of memory bandwidth.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: December 1, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ying Li, Xiaofei Li, Yanjuan Zhan, Zhehong Qian, Buying Du
  • Patent number: 10852947
    Abstract: A system and method reduces cleaning overhead in a storage array by establishing owner groups for selectively organizing memory page groups. The method generates a metadata lookup structure to correlate a disk address of the real-time data generated to a logical block address on the select storage volume. Further, the method establishes a current state of the select storage volume as a first owner group that receives reference access to the logical block address associated with the memory page group. The method selectively generates a memory snapshot of the current state of the select storage volume to form a subsequent owner group. Additionally, the method enables the first owner group and the subsequent owner group to reference the logical block address that is associated with the memory page group until a real-time data write provides a new logical block address that is associated with a new memory page group.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: December 1, 2020
    Assignee: Dell Products, L.P.
    Inventors: Laco S. Harvell, Shari A. Vietry
  • Patent number: 10846237
    Abstract: Methods and apparatus for locking at least a portion of a shared memory resource. In one embodiment, an electronic device configured to lock at least a portion of a shared memory is disclosed. The electronic device includes a host processor, at least one peripheral processor and a physical bus interface configured to couple the host processor to the peripheral processor. The electronic device further includes a software framework that is configured to: attempt to lock a portion of the shared memory; verify that the peripheral processor has not locked the shared memory; when the portion of the shared memory is successfully locked via the verification that the peripheral processor has not locked the portion of the shared memory, execute a critical section of the shared memory; and otherwise attempt to lock the at least the portion of the shared memory at a later time.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: November 24, 2020
    Assignee: Apple Inc.
    Inventors: Vladislav Petkov, Haining Zhang, Karan Sanghi, Saurabh Garg
  • Patent number: 10846214
    Abstract: To operate a nonvolatile memory system including a nonvolatile memory device and a memory controller, a mapping memory is divided into a plurality of mapping memory regions where the mapping memory stores mapping data representing a mapping relation between a logical address of a host device and a physical address of the nonvolatile memory device. Occupation information representing whether the mapping data are stored in each mapping memory region of the plurality of mapping memory regions are provided. Based on the occupation information, user data are stored in a corresponding mapping memory region of the plurality of mapping memory regions in which the mapping data are not stored.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Hoon Kim, Young-Sik Lee, Kang-Ho Roh
  • Patent number: 10831373
    Abstract: One embodiment provides a system including a computer processor, a computer-readable hardware storage device, and program code embodied with the computer-readable hardware storage device for execution by the computer processor to implement a method that includes selecting a first blob for reclamation from a first data center. The first blob includes multiple erasure code groups. A first message is sent to a second data center indicating the first blob is to be reclaimed. A second message is sent to the second data center after reclaiming the first blob in the first data center. A global reclamation complete message is received from the second data center. The global reclamation complete message indicates a second blob in the second data center has been reclaimed. The global reclamation complete message is sent in response to the second data center receiving a local reclamation complete message from a third data center.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Hetzler, Wayne C. Hineman
  • Patent number: 10824554
    Abstract: A non-volatile memory (NVM) apparatus and an iteration sorting method thereof are provided. The NVM apparatus performs the iteration sorting method to select one target block from a plurality of blocks of a NVM, and to perform a management operation on the target block. The iteration sorting method includes: selecting a plurality of candidate blocks among the blocks of the NVM to join into a sorting set, sorting all of the candidate blocks in the sorting set according to metadata, picking one candidate block with maximum (or minimum) metadata from the sorting set to serve as the target block, and keeping M candidate blocks in the sorting set and discarding the rest of the candidate blocks from the sorting set.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: November 3, 2020
    Assignee: VIA Technologies, Inc.
    Inventors: Ying Yu Tai, Jiangli Zhu
  • Patent number: 10824362
    Abstract: Various examples described herein provide for migrating a file between a non-persistent memory file system and a persistent memory file system. In particular, some examples detect, on a non-persistent memory file system, a file that has been memory-mapped while being accessed from the non-persistent memory file system by a computer system, and the detected file is migrated from the non-persistent memory file system to the persistent memory file system.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: November 3, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Douglas L. Voigt, Meng Zou
  • Patent number: 10817185
    Abstract: A device, memory, method and system directed to fast data storage on a block storage device that reduces operational wear on the device. New data is written to an empty write block with a number of write blocks being reused. A location of the new data is tracked. Metadata associated with the new data is written. A lookup table may be updated based in part on the metadata. The new data may be read based the lookup table configured to map a logical address to a physical address.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 27, 2020
    Inventors: Douglas Dumitru, Samuel J. Anderson
  • Patent number: 10817196
    Abstract: A method for generating a data directory can include allocating a first page for storing a first segment of a log recording changes applied to data subsequent to a checkpoint. When the first page reaches maximum capacity, a second page can be allocated for storing a second segment of the log. A third page can be allocated for storing a first page list that includes a first page reference to the second data page. A fourth page serving as a restart page can be updated. The fourth page can store a second page list of data pages storing the data directory. The fourth page can be updated to add, to the second page list, a second page reference to the data page. Crash recovery at the computing node can be performed based on the data directory. Related systems and articles of manufacture are also provided.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: October 27, 2020
    Assignee: SAP SE
    Inventor: Ivan Schreter
  • Patent number: 10810142
    Abstract: Apparatuses and method for an integrated circuit device are described. In an apparatus thereof, there is a plurality of memory controllers coupled to a plurality of memory banks. A network of switches is coupled to the plurality of memory controllers. A plurality of data processing devices is coupled to the network of switches and is configured to generate memory requests. A network controller is coupled to the network of switches and is configured to queue the memory requests and selectively issue requests to memory from the memory requests queued responsive to corresponding response times associated with the plurality of memory banks.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: October 20, 2020
    Assignee: XILINX, INC.
    Inventor: Suryanarayana Murthy Durbhakula
  • Patent number: 10802895
    Abstract: A method and an apparatus for determining a usage level of a memory device to notify a running application to perform memory reduction operations selected based on the memory usage level are described. An application calls APIs (Application Programming Interface) integrated with the application codes in the system to perform memory reduction operations. A memory usage level is determined according to a memory usage status received from the kernel of a system. A running application is associated with application priorities ranking multiple running applications statically or dynamically. Selecting memory reduction operations and notifying a running application are based on application priorities. Alternatively, a running application may determine a mode of operation to directly reduce memory usage in response to a notification for reducing memory usage without using API calls to other software.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: October 13, 2020
    Assignee: Apple Inc.
    Inventors: Matthew G. Watson, James Michael Magee
  • Patent number: 10798169
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device detects memory error(s) associated with memory device(s) of set(s) of storage units (SUs). The computing device processes the memory error(s) to generate a rebuilding priority level for at least some EDS(s) and establishes an EDS scanning rate. The computing device scans the EDS(s) based on the EDS scanning rate. When an EDS error is detected, the computing device updates the rebuilding priority level to generate an updated rebuilding priority level for the at least some of the set of EDSs and facilitates generation at least one rebuilt EDS for the EDS error based on the updated rebuilding priority level.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: October 6, 2020
    Assignee: PURE STORAGE, INC.
    Inventor: Thomas D. Cocagne
  • Patent number: 10795615
    Abstract: Embodiments of the present disclosure provide a storage management method and device. The method comprises: obtaining an attribute and access information of a file stored in storage at a first level in a hierarchical storage system, the attribute of the file indicating a size of the file, and the access information indicating an access frequency of the file; determining necessity of migrating the file based on the attribute of the file and the access information; and in response to the necessity exceeding a predetermined threshold, migrating the file to storage at a second level in the hierarchical storage system, the second level being different from the first level. Embodiments of the present disclosure further disclose a corresponding device.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: October 6, 2020
    Assignee: EMC IP Holding Company, LLC
    Inventors: Shuo Lv, Wilson Hu, Bean Zhao, Chao Han, Eileen Gu
  • Patent number: 10776285
    Abstract: In an active-active system, if write lock permission is granted to a second storage array, a first storage array sends to-be-written data and a lock revocation request together to a lock server; the lock server sends a lock revocation request carrying the to-be-written data to the second storage array; after storing the to-be-written data, the second storage array sends a lock revocation success message to the lock server; the lock server gives the write lock permission to the first storage array; and the first storage array obtains the write lock permission and stores the to-be-written data.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: September 15, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Lei Chen, Keji Huang
  • Patent number: 10776273
    Abstract: A semiconductor memory system and an operating method thereof include a controller; and a memory device including a memory page manager, Nand pages, and multiple cache pages, wherein the Nand pages include current Nand pages and next Nand pages, wherein the current Nand pages is corresponding to a read command received from the controller, the memory page manager is configured to manage correlation of the Nand pages and the multiple cache pages, predict next Nand pages in accordance at least in part with the read command, the current Nand pages, or a combination thereof, and send the Nand pages to the controller, and the multiple cache pages contain pages loaded from the Nand pages.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Yungcheng Lo
  • Patent number: 10768836
    Abstract: A method for page based data persistence can include storing data associated with a state machine at a computing node. The data can be stored by at least allocating a first data page for storing the data. In response to the allocation of the first data page, a first page reference to the first data page can be added to a first page list in an in-memory buffer at the computing node. When the in-memory buffer reaches maximum capacity, a second data page can be allocated for storing the first page list. A second page reference to the second data page can be added to a second page list in the in-memory buffer. Related systems and articles of manufacture, including computer program products, are also provided.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: September 8, 2020
    Assignee: SAP SE
    Inventor: Ivan Schreter
  • Patent number: 10768823
    Abstract: Methods, systems, and programs are presented for controlling the flow of data into a device in the presence of writes that are unaligned along boundaries associated with a block size. One method includes operations for identifying admission data rates for volumes, and for tracking a utilization rate of a memory that stores data of incoming writes. The method determines if incoming writes include unaligned data. When the memory utilization rate is above a first threshold, a first flow control is applied that includes a reduction of admission rates of volumes having unaligned writes while maintaining admission rates of volumes without unaligned writes. When the utilization rate is above a second threshold that is greater than the first threshold, a second flow control is applied in addition to the first flow control. The second flow control includes a reduction of a system admission rate for all incoming writes.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: September 8, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gurunatha Karaje, Mandar Samant, Sourabh Yerfule, Zhaosheng Zhu, Vanco Buca
  • Patent number: 10761769
    Abstract: A memory sub-system is disclosed that makes accessible accumulated memory temperature statistics in relation to a target memory portion. This can be accomplished by maintaining one or more hold variables and one or more accumulation variables. The accumulation variables can be iteratively updated upon triggers such as a timer expiration or I/O event. Updating the accumulation variables can include obtaining a current temperature and tracking one or more of: a maximum, minimum, and mean temperature across the iterations. An accumulation value can track how many times the accumulation variables have been updated. When the accumulation value reaches an accumulation action threshold, the current state of the accumulation variables can be used to update the hold variables. The accumulation value and accumulation variables can then be reset and used for accumulation of additional temperature statistics.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gerald L. Cadloni, Bruce A. Liikanen
  • Patent number: 10761979
    Abstract: A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Hugh Wilkinson, William R. Wheeler, Debra Bernstein