Patents Examined by Tung X. Nguyen
  • Patent number: 11686765
    Abstract: Provided is a die extraction method, comprising the following steps: removing solder balls; polishing a front side of the sample to remove a part on a front side of the target die, and retain a part of a die attach film (DAF) layer on the front side of the target die and a bonding wire located in the part; attaching the front side of the sample to the polishing jig and flattening the sample and the polishing jig by the flattener; polishing the back side of the sample to remove a part on a back side of the target die, and retain a DAF layer on the back side of the target die; removing the DAF and a packaging material remaining on the sample to obtain the target die; and attaching the back side of the target die to a glass slide, thus completing extraction of the target die.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: June 27, 2023
    Inventor: Kun Wang
  • Patent number: 11686762
    Abstract: A multi-prober chuck assembly and channel are provided. The multi-prober chuck assembly, according to one embodiment of the present invention, comprises: a chuck for supporting a wafer; a probe card structure coupled to the top part of the chuck; a heater for heating the chuck under the chuck; a conductive guard plate spaced apart from the heater below the heater; and a body part positioned under the chuck so that the heater and the guard plate are positioned inside the body part, wherein the probe card structure and the body part are coupled mechanically to form a cartridge-type structure.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: June 27, 2023
    Assignee: Korea Institute of Industrial Technology
    Inventors: Kyung Tae Nam, Seung Joon Lee, Kwang Hee Lee
  • Patent number: 11674998
    Abstract: A contactor assembly for a testing system is disclosed. The assembly includes a contact having a contact tail and a housing having a top surface and a bottom surface. A slot extends through the housing from the top surface to the bottom surface and defines a first inner side wall of the housing and a first inner end wall. The contact is receivable in the slot. The contact tail includes a sloped terminus. A retainer is disposed on the first inner side wall. When the sloped terminus is engaged with the first inner end wall, at least a portion of the retainer overlaps with the contact forming at an overlapping area in a cross-sectional view, thereby preventing removal of the contact from the top side of the housing.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: June 13, 2023
    Assignee: Johnstech International Corporation
    Inventors: Bob Chartrand, David Johnson, Brian Sheposh, Mike Andres
  • Patent number: 11668767
    Abstract: The present disclosure relates to a magnetic field sensor circuit including at least one coil for measuring a magnetic field, a first stage amplifier circuit coupled to the coil and having a first transfer function with a pole at a first frequency, and a second stage amplifier circuit coupled to an output of the first stage amplifier circuit and having a second transfer function with a zero at the first frequency. In some embodiments, a temperature dependent frequency drift of the pole of the first transfer function corresponds to a temperature dependent frequency drift of the zero of the second transfer function.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: June 6, 2023
    Assignee: Infineon Technologies AG
    Inventors: Mario Motz, Qinwen Fan, Amirhossein Jouyaeian, Kofi Makinwa
  • Patent number: 11668746
    Abstract: Systems, devices, and methods for performing a non-contact electrical measurement (NCEM) on a NCEM-enabled cell included in a NCEM-enabled cell vehicle may be configured to perform NCEMs while the NCEM-enabled cell vehicle is moving. The movement may be due to vibrations in the system and/or movement of a movable stage on which the NCEM-enabled cell vehicle is positioned. Position information for an electron beam column producing the electron beam performing the NCEMs and/or for the moving stage may be used to align the electron beam with targets on the NCEM-enabled cell vehicle while it is moving.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: June 6, 2023
    Assignee: PDF SOLUTIONS, INC.
    Inventors: Indranil De, Marian Mankos, Dennis Ciplickas, Christopher Hess, Jeremy Cheng, Balasubramanian Murugan, Qi Hu
  • Patent number: 11668744
    Abstract: A contact for burning-in and testing a semiconductor IC and a socket device including the contact are proposed. The contact includes: an upper terminal part (111) having an upper tip part (111b) at an upper end part thereof; a lower terminal part (112) having a lower tip part (112c) at a lower end part thereof and provided on the same axis as the upper terminal part (111); and an elastic part (113) elastically supporting the upper terminal part (111) and the lower terminal part (112), wherein the upper terminal part (111) and the lower terminal part (112) include a shoulder part (111a) and a shoulder part (112a), respectively, formed by protruding therefrom in width directions thereof, and the elastic part (113) has a third width (w3), and includes a first strip (113a) and a second strip (113b).
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: June 6, 2023
    Inventors: Dong Weon Hwang, Logan Jae Hwang, Jae Baek Hwang
  • Patent number: 11662376
    Abstract: An on-die early lifetime failure detection system with a reliability mechanism isolation circuit provides an early lifetime failure detection. The system measures and monitors reliability at time-0 (t0) and end-of-life. The measurements enable detection of latent reliability or marginality issues during the lifetime of the product. The system includes: a stress controller to adjust voltage for a power supply and voltage for a ground supply in accordance with one or more sensors; and an aging detector circuitry coupled to the stress controller, wherein the aging detector circuitry comprises a ring oscillator having delay stages, wherein each delay stage comprises an aging monitor circuitry, wherein the stress controller to adjust voltage for a power supply and voltage for a ground supply of the delay stage.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: May 30, 2023
    Assignee: Intel Corporation
    Inventors: Ketul B. Sutaria, Balkaran Gill
  • Patent number: 11662371
    Abstract: Semiconductor devices, and in particular semiconductor devices for improved resistance measurements and related methods are disclosed. Contact structures for semiconductor devices are disclosed that provide access to resistance measurements with reduced influence of testing-related resistances, thereby improving testing accuracy, particularly for semiconductor devices with low on-resistance ratings. A semiconductor device may include an active region and an inactive region that is arranged along a perimeter of the active region. The semiconductor device may be arranged with a topside contact to provide access for resistance measurements, for example Kelvin-sensing resistance measurements. Related methods include performing resistance measurements from a topside of the semiconductor device, even when the active region of the semiconductor device forms a vertical contact structure.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: May 30, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: James Richmond, Edward Robert Van Brunt
  • Patent number: 11664788
    Abstract: A chip, a self-calibration circuit and method for chip parameter offset upon power-up are disclosed. The circuit includes a counting circuit, a calibration data latch circuit, a calibration data selection circuit and a parameter calibration circuit. The counting circuit outputs a sequentially scanned counting signal when receiving a valid enabling signal. The calibration data latch circuit latches the counting signal when receiving a valid latch signal. The calibration data selection circuit selects the counting signal latched by the calibration data latch circuit as a calibration signal when receiving the valid latch signal, otherwise selects the counting signal currently outputted as the calibration signal. The parameter calibration circuit implements a parameter calibration based on the calibration signal in a calibration mode, while outputs the valid latch signal when the parameter calibration satisfies a preset requirement.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: May 30, 2023
    Assignee: Fremont Micro Devices Corporation
    Inventors: Jianfeng Liu, Yuquan Huang, Dennis Sinitsky
  • Patent number: 11662378
    Abstract: Detection circuitry for an integrated circuit (IC) includes voltage divider circuitry, comparison circuitry, and calibration circuitry. The voltage divider circuitry receives a power supply signal and output a first reference voltage signal and a supply voltage signal based on the power supply signal. The comparison circuitry compares the first reference voltage signal and the supply voltage signal to generate an output signal. The calibration circuitry alters one or more parameters of the voltage divider circuitry to increase a voltage value of the supply voltage signal based on the comparison of the first reference voltage signal with the supply voltage signal.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: May 30, 2023
    Assignee: XILINX, INC.
    Inventors: Sourabh Sharma, Sree Rama Krishna Chaithnya Saraswatula, Santosh Yachareni
  • Patent number: 11656269
    Abstract: An apparatus comprises a load resistance connectable in series with the electronic sensor to form a series resistance of the load resistance and the internal impedance of the electronic sensor; an excitation circuit configured to apply a predetermined voltage to a circuit element; and a measurement circuit configured to: initiate applying the predetermined voltage to the series resistance and determining the series resistance; initiate applying the predetermined voltage to the load resistance and determining the load resistance; and calculate the internal impedance of the sensor using the determined series resistance and the load resistance, and provide the calculated internal impedance to a user or process.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: May 23, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: GuangYang Qu, Yincai Tony Liu, Baotian Hao, Hanqing Wang, Hengfang Mei, Rengui Luo, Yimiao Zhao, Junbiao Ding
  • Patent number: 11656273
    Abstract: Embodiments of the present invention provide systems and methods for performing automated device testing at high power using ATI-based thermal management that substantially mitigates or prevents the pads and pins thereof from being burned or damaged. In this way, the lifespan of the testing equipment is improved and the expected downtime of testing equipment is substantially reduced, while also reducing cost of operation.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: May 23, 2023
    Assignee: Advantest Test Solutions, Inc.
    Inventors: Gregory Cruzan, Karthik Ranganathan, Mohammad Ghazvini, Paul Ferrari, Samer Kabbani, Todd Berk
  • Patent number: 11650245
    Abstract: A signal transmission circuit board includes a main body and a first connecting unit connected with the main body. The first connecting unit includes a test pin area and an avoidance area adjacent to the test pin area, and the avoidance area is free of test pins.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: May 16, 2023
    Assignee: Yungu (Gu'an) Technology Co., Ltd.
    Inventors: Genmao Huang, Gusheng Xu, Li Lin, Bo Yuan, Siming Hu
  • Patent number: 11644505
    Abstract: In a measurement system, a signal probing circuit may provide probed signals by probing voltages and currents and/or incident and reflected waves at a port of a device under test (DUT). A multi-channel receiver structure may include receivers that receive two probed signals from the signal probing hardware circuit, each receiver having its own sample clock derived from a master clock and further having a respective digitizer for digitizing a corresponding one of the two probed signals. A synchronization block, external to the receivers and including a reference clock derived from the master clock, may enable the two probed signals to be phase coherently digitized across the receivers by synchronizing the respective sample clocks of the receivers while the reference clock is being shared with the receivers. A signal processing circuit may then process the phase coherently digitized probed signals.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: May 9, 2023
    Assignee: National Instruments Ireland Resources Limited
    Inventor: Marc Vanden Bossche
  • Patent number: 11644488
    Abstract: A direct current (DC) power rail probe includes a single-ended probe tip, and a two-path circuit having an input coupled to the single-ended probe tip and an output configured for connection to measurement equipment such as an oscilloscope. The two-path circuit includes an alternating current (AC) path in parallel with a feed-forward (FF) path, the AC path including a capacitive element, and the FF path including a series connection of at least one resistive element and an amplifier. The probe tip and two-path circuit are selectively operable in a non-attenuating mode and an attenuating mode.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: May 9, 2023
    Inventors: Edward Vernon Brush, Michael Thomas McTigue
  • Patent number: 11639956
    Abstract: A test socket comprising a guide plate with a lower surface engaged with an upper surface of a main test structure, the guide plate further including an upper surface which is parallel to the lower surface and an opening extending through the guide plate, the main test structure includes a body with one or more apertures through the upper surface and one or more probes mounted within the main test structure, the probes including a front end which extends through the apertures for engagement by a lead or terminal pad of a device to be tested, and a tail end which is secured within the main test structure by an elastomeric material.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: May 2, 2023
    Assignee: UI Green Micro & Nano Technologies Co Ltd
    Inventors: Mark Zhang, Arvin Guo, Jeff Tamasi, Steve Liu
  • Patent number: 11639958
    Abstract: A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and the pad voltage terminal. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The fourth transistor is in a second well different from the first well, and is separated from the first well in a first direction.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: May 2, 2023
    Inventors: Hsiang-Hui Cheng, Chia-Jung Chang
  • Patent number: 11639946
    Abstract: According to one embodiment, a sensor includes a base including a first face including a first face region, and a first structure body fixed to the first face region. The first structure body includes a first support portion fixed to the first face region, a second support portion fixed to the first face region, a first movable portion, and a first fixed electrode fixed to the first face region. The first movable portion is supported by the first and second support portions and apart from the base in a first direction crossing the first face region. The first movable portion includes a first movable electrode facing the first fixed electrode, and a first conductive member. A first current flows the first conductive member along a second direction crossing the first direction. A first gap is provided between the first fixed electrode and the first movable portion.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: May 2, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroaki Yamazaki
  • Patent number: 11639949
    Abstract: A Rogowski coil is used for determining the magnitude of the electrical current of a conductor of a low-voltage AC circuit, which outputs an analogue voltage which is equivalent to the magnitude of the electrical current of the conductor. The Rogowski coil is connected to an analogue integrator, which is followed by an analogue-digital converter, which converts the integrated analogue voltage into a digital signal which is further processed by a microprocessor in such a way that the phase shift generated by the Rogowski coil and the components connected downstream of the Rogowski coil is compensated such that there are in-phase current values for the detection of error situations in order to protect the low-voltage AC circuit, in particular for a low-voltage power switch or an arc fault detection unit.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: May 2, 2023
    Assignee: Siemens Aktiengesellschaft
    Inventors: Joerg Meyer, Peter Schegner, Karsten Wenzlaff
  • Patent number: 11639972
    Abstract: The present invention relates to a sensor suite comprising at least one sensor. More particularly, the present invention relates to a sensor suite for measuring absolute and/or relative position, location and orientation of an object on or in which the sensor suite is employed. The present invention further relates to improved, novel sensor types for use in the sensor suite. More particularly, the present invention relates to an improved, novel magnetometer that is self-calibrating and scalable. Still more particularly, the present invention relates to such a magnetometer that is miniaturized. Further embodiments of the present invention relate to systems and methods for providing location and guidance, and more particularly for providing location and guidance in environments where global position systems (GPS) are unavailable or unreliable (GPS denied and/or degraded environments).
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: May 2, 2023
    Assignee: Orbital Research Inc.
    Inventors: Anthony Opperman, Edward J. Rapp