Patents Examined by Tung X. Nguyen
  • Patent number: 12216151
    Abstract: A measurement instrument for testing a DUT comprises a common port configured to be connectable to a signal output of the DUT for receiving a forward-travelling signal from the DUT. The measurement instrument further comprises a signal line connected to the common port, a signal analysis circuit and a signal generator circuit. The signal analysis circuit receives the forward-travelling signal from the common port. The signal analysis circuit is configured to analyze the forward-travelling signal in order to assess a performance of the DUT. The signal generator circuit is connected to the signal line and is configured to generate a backward-travelling signal that is forwarded to the common port. The signal generator circuit comprises a reference signal input configured to receive a reference signal from a reference signal generator. The signal generator circuit is configured to generate the backward-travelling signal based on the reference signal.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: February 4, 2025
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Paul Gareth Lloyd, Markus Loerner
  • Patent number: 12216154
    Abstract: A stand-alone active thermal interposer device for use in testing an unpackaged integrated circuit device under test (DUT), the active thermal interposer device includes a body layer having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the body layer, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the body layer is disposed adjacent to an interface surface of the DUT during testing of the DUT.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: February 4, 2025
    Assignee: Advantest Test Solutions, Inc.
    Inventors: Samer Kabbani, Paul Ferrari, Ikeda Hiroki, Kiyokawa Toshiyuki, Gregory Cruzan, Karthik Ranganathan, Todd Berk, Ian Williams, Mohammad Ghazvini, Thomas Jones
  • Patent number: 12210054
    Abstract: One example includes a method for trimming a reference voltage in an integrated circuit (IC). The method includes fabricating the IC that is configured to generate the reference voltage based on a circuit design. The fabricated IC includes a pair of conductive input/output (I/O) leads and a resistance test switch system coupled between the conductive I/O leads. The method also includes coupling the conductive I/O leads of the fabricated IC to a circuit test fixture and setting the resistance test switch system to a test mode via automated testing equipment (ATE) associated with the circuit test fixture. The method also includes providing a test signal to the conductive I/O leads and measuring a resistance between the conductive I/O leads in response to the test signal. The method further includes trimming the reference voltage based on the measured resistance.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: January 28, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Kar Hou Chai
  • Patent number: 12210075
    Abstract: A tunnel magnetoresistance (TMR) sensing element includes a layer stack having a tantalum-nitride (TaN) layer; a reference layer system; a magnetic free layer having a magnetically free magnetization; and a tunnel barrier layer arranged between the reference layer system and the magnetic free layer. The reference layer system includes a pinned layer having a fixed pinned magnetization; a reference layer having a having a fixed reference magnetization; a coupling interlayer arranged between the pinned layer and the reference layer; and a natural antiferromagnetic (NAF) layer comprising iridium-manganese (IrMn), wherein the NAF layer is formed in direct contact with the TaN layer, wherein the NAF layer is configured to hold the fixed pinned magnetization in a first magnetic orientation and hold the fixed reference magnetization in a second magnetic orientation, and wherein the direct contact of the NAF layer with the TaN layer increases a blocking temperature of the NAF layer.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: January 28, 2025
    Assignee: Infineon Technologies AG
    Inventor: Bernhard Endres
  • Patent number: 12202356
    Abstract: A system includes: a module configured to: compare operating parameters with predetermined thresholds, respectively; and set indicators for the operating parameters based on the comparisons, respectively; a module configured to: set a first indicator to a first state when all of first ones of the indicators are in a first state; and set the first indicator to a second state when at least one of the first ones of the indicators is in a second state; a module configured to: set a second indicator to a first state when at least one of second ones of the indicators are in a first state; and set the second indicator to a second state when all of the second ones of the indicators are in a second state; and a module configured to indicate whether an electric motor is degraded based on at least one of the first and second indicators.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: January 21, 2025
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Noah Jon Lovins-Wilusz, Jeffrey M. Pieper, Vino Mathew
  • Patent number: 12203749
    Abstract: The invention relates to a chain elongation monitoring device having a first differential transformer, a second differential transformer, and a control for recording the measured values, wherein the second differential transformer is arranged at a fixed distance from the first differential transformer, and a method for operating the chain elongation monitoring device.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: January 21, 2025
    Inventors: Thomas Wolf, Josef Siraky
  • Patent number: 12196791
    Abstract: A highly accurate feature extraction is performed on a signal with temporal variation in amplitude, and this signal is restored to detect a state of a transmission source (output source) of this signal to be normal or abnormal. A signal processing method includes: separating a signal X into an oscillation signal with a constant amplitude X1 and a signal with temporal variation in amplitude X2, the separating performed by a signal separator; performing processing of dimensionality reduction, compression, or the like, on the oscillation signal X1 so as to extract a feature value (information) included in the oscillation signal X1; and outputting a restored signal X1? that is restored from the oscillation signal X1 by performing processing inverse to the processing of dimensionality reduction, compression, or the like, based on the extracted feature value, performing the processing, the inverse processing, and the outputting performed by a signal X1 restorer.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: January 14, 2025
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakagawa, Soichiro Tanaka, Masato Kunitomo, Kazuaki Tokunaga
  • Patent number: 12196805
    Abstract: A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: January 14, 2025
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Patent number: 12196807
    Abstract: A package substrate may include a circuit and a leaky surface wave launcher. The circuit may perform engineering tests and end-user operations using sideband signals. The leaky surface wave launcher may perform near field wireless communication. The leaky surface wave launcher may include a via and a strip line. The via may be electrically coupled to the circuit. The via may provide the sideband signals to and receive the sideband signals from the circuit. The strip line may be electrically coupled to the via. The strip line may be excited by the sideband signals to wirelessly couple the leaky surface wave launcher with an external device. The strip line and the via may be unbalanced such that the strip line generates a leaky wave that propagates at least a portion of the package substrate and an environment proximate the package substrate.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: January 14, 2025
    Assignee: Intel Corporation
    Inventors: Zhen Zhou, Renzhi Liu, Jong-Ru Guo, Kenneth P. Foust, Jason A. Mix, Kai Xiao, Zuoguo Wu, Daqiao Du
  • Patent number: 12196790
    Abstract: This disclosure relates generally to an energy metering assembly configured to measure current and voltage of a one or more primary conductors, the energy metering assembly comprising a core; a coil having a plurality of turns, the coil being positioned around the core when securing the core to the one or more primary conductors; a voltage sensor, the voltage sensor being configured to sense a voltage of a one or more primary conductors; and a controller coupled to the coil and the voltage sensor, the controller being configured to determine a voltage of the one or more primary conductors, determine a current of the one or more primary conductors, and responsive to determining the voltage and the current, determine the power carried by the one or more primary conductors.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: January 14, 2025
    Assignee: SCHNEIDER ELECTRIC USA, INC.
    Inventors: Colin N. Gunn, Stewart John Harding, Benedikt Theodor Huber
  • Patent number: 12195861
    Abstract: An example test station assembly of a cathodic protection monitoring assembly includes a face plate including a plurality of openings. In addition, the test station assembly includes a plurality of test posts to pass through the plurality of openings. Further, the test station assembly includes a plurality of electrically non-conductive identification indicators to connect to the plurality of test posts on the face plate. Each of the plurality of identification indicators including one or more identifying characteristics to identify a corresponding voltage source of a plurality of underground voltage sources associated with an at least partially buried structure, a cathodic protection system for the buried structure, or the cathodic protection monitoring assembly. Still further, the test station assembly includes a plurality of electrical conductors to electrically connect the plurality of test posts to the plurality of underground voltage sources.
    Type: Grant
    Filed: November 2, 2023
    Date of Patent: January 14, 2025
    Assignee: MARATHON PETROLEUM COMPANY LP
    Inventors: Ryan Grant Ell, Brandon Daniel Hall
  • Patent number: 12180597
    Abstract: An example test station assembly of a cathodic protection monitoring assembly includes a face plate including a plurality of openings. In addition, the test station assembly includes a plurality of test posts to pass through the plurality of openings. Further, the test station assembly includes a plurality of electrically non-conductive identification indicators to connect to the plurality of test posts on the face plate. Each of the plurality of identification indicators including one or more identifying characteristics to identify a corresponding voltage source of a plurality of underground voltage sources associated with an at least partially buried structure, a cathodic protection system for the buried structure, or the cathodic protection monitoring assembly. Still further, the test station assembly includes a plurality of electrical conductors to electrically connect the plurality of test posts to the plurality of underground voltage sources.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: December 31, 2024
    Assignee: MARATHON PETROLEUM COMPANY LP
    Inventors: Ryan Grant Ell, Brandon Daniel Hall
  • Patent number: 12181513
    Abstract: A control device controls a contact probe in synchronization with a pulse-controlled light having a predetermined wavelength, a measurement instrument measures a characteristic of a sample to be inspected or an analysis sample, and a circuit constant or a defect structure of the sample to be inspected is estimated based on a circuit model created by an electric characteristic analysis device configured to generate the circuit model based on a value measured by the measurement instrument and a detection signal of secondary electrons detected by the charged particle beam device.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: December 31, 2024
    Assignee: Hitachi High-Tech Corporation
    Inventors: Shota Mitsugi, Yohei Nakamura, Daisuke Bizen, Junichi Fuse, Satoshi Takada, Natsuki Tsuno
  • Patent number: 12174250
    Abstract: A method for checking a Design for Test (DFT) circuit includes: transmitting a control signal to the DFT circuit to determine test mode signals output by the DFT circuit, with the DFT circuit being configured to sequentially select multiple address latches according to the control signal to output the test mode signals; analyzing the test mode signals to determine whether the multiple address latches in the DFT circuit have an error; and outputting a simulation result report.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: December 24, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Teng Shi, Kang Zhao
  • Patent number: 12174268
    Abstract: A system for detecting a faulty connection in an earth grid 104 is provided. The system includes a current injection device 102 to provide an input current with off grid frequency to the earth grid 104 through a reference riser 112. The riser under test 110 is connected with the earth grid 104 to receive the input current with off grid frequency and the earth grid 104. The system includes a first current measuring device that measures, at the riser under test 110, a first current that is received from the earth grid 104 and a second current measuring device that measures, at the riser under test 110, a second current that is received from the earth grid 104. The second current measuring device compares the first current and the second current to determine a faulty connection in the riser under test 110.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: December 24, 2024
    Inventor: Prashanth Belur Gururaja Rao
  • Patent number: 12174223
    Abstract: An apparatus and a tool for installation of a measurement coil. The apparatus includes a tool and a holder. The tool includes a first portion and a second portion at least partially surrounding the first portion. The first portion is configured to receive a conductor and the second portion is configured to hold a measurement coil. The holder is configured to be detachably attached to the tool, wherein the holder is to be employed to install the tool holding the measurement coil onto a conductor. The first portion is configured to snap fit onto the conductor during installation, and the measurement coil at least partially surrounds the conductor when installed.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: December 24, 2024
    Assignee: Safegrid Oy
    Inventors: Jyrki Penttonen, Jussi Hakunti
  • Patent number: 12174266
    Abstract: A circuit for detecting a leakage current in a semiconductor element includes a setting circuit and a detector. The semiconductor element includes a first terminal at a high-potential-side of the semiconductor element, a second terminal at a low-potential-side of the semiconductor element, and a control terminal. The control terminal receives a signal for controlling a conduction state between the first terminal and the second terminal. The setting circuit sets a duration during which a charging current flows to the control terminal as an undetectable duration, in response to turning on the semiconductor element. The detector outputs a detected signal based on a condition that the leakage current flowing from the control terminal to the second terminal, after the undetectable duration has been elapsed.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: December 24, 2024
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation
    Inventors: Junichi Hasegawa, Akimasa Niwa
  • Patent number: 12169218
    Abstract: Circuitry, systems, and methods for fault detection and reporting comprise a fault detection circuit configured to detect one or more fault conditions that cause a state change in a fault pin voltage representative of a transceiver failure. Once the state of the fault pin voltage changes, a transceiver input generates a fault detection code. In embodiments, in response to the transceiver input receiving a first signal, the fault detection code is shifted to a transceiver output that may communicate the fault detection code to a controller. Once the transceiver input receives a second signal, the fault pin voltage may be reset to clear the fault detection code before resuming operations, including detecting additional fault conditions as they arise.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: December 17, 2024
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Ling Liu, Robert Gee
  • Patent number: 12163986
    Abstract: A system may include amplifier circuitry configured to drive an electromagnetic load with a driving signal and a processing system communicatively coupled to the electromagnetic load and configured to compensate for current-sensing error of the processing system caused by feedback circuitry of the amplifier circuitry.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: December 10, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: Anand Ilango, Siddharth Maru, Tejasvi Das, John L. Melanson
  • Patent number: 12163996
    Abstract: A system for testing an electronic circuit board test coupon, including a test chamber. The test chamber can have at least one port through which a port extension member holding a test coupon can be inserted, minimizing air flow between the interior space of the test chamber and the surrounding area to adequately maintain elevated heat and humidity conditions within the test chamber.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: December 10, 2024
    Assignee: Magnalytix, LLC
    Inventors: Michael L. Bixenman, Thomas M. Forsythe, Mark McMeen, Colin Langley, James Perigen, Bobby Glidwell