Abstract: An inspection apparatus includes: a plurality of inspection devices configured to respectively inspect electronic devices of inspection objects on a plurality of chuck tops; a measurement device configured to measure height positions of a plurality of points on a surface of each of the plurality of chuck tops, which are respectively disposed to correspond to the plurality of inspection devices, or to measure distances in a height direction from a measurement reference point to the plurality of points; a calculation device configured to calculate adjustment amounts in the height direction at the plurality of points of each chuck top, based on the height positions of the plurality of points or the distances in the height direction from the measurement reference point to the plurality of points; and an adjustment mechanism configured to adjust, for each chuck top, an angle of the respective chuck top based on the adjustment amounts.

Abstract: The invention relates to a broadband high power amplifier that comprises a signal input adapted to receive an input signal, at least one amplifier stage adapted to amplify the received input signal, a signal output adapted to output the signal amplified by the at least one amplifier stage as an output signal, a monitoring unit adapted to monitor signal characteristics of the input signal and the output signal and a control unit adapted to operate the at least one amplifier stage at an optimal operating point depending on the current signal characteristics monitored by said monitoring unit.

Abstract: A voltage tracking circuit includes a first, second, third and fourth transistor. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and the pad voltage terminal. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. At least the third transistor is in a second well different from the first well, and is separated from the first well in a first direction.

Abstract: The present invention concerns a heating assembly (10, 15) for generating heat in order to carry out temperature-dependent tests on an electronic component (3, 200) arranged inside a socket (2), the heating assembly (10, 15) comprising: A heating device (10) comprising an electrically conductive material (25) in such a manner as to allow the passage of an electrical current to produce heat. According to the invention, the assembly further comprises: A covering (15) of a thermally insulating material suitable for containing said heating device (10) inside, the covering having at least one opening at one side for allowing the heat diffusion through said opening; Fastening means for fastening said covering (15) to a support surface (5B), in such a manner that, while used, the heating device (10), arranged inside said covering (15), faces said support surface (5B) through said opening.

Abstract: A device having an impedance measurement circuit that allows for reduction of flicker noise can be implemented in a variety of applications. A carrier suppression technique can be implemented that substantially removes the carrier signal with removal of noise artifacts associated with the carrier signal from sidebands of the carrier signal. Carrier suppression in an AC impedance measurement circuit can be implemented by sensing a carrier signal of the measurement circuit at a transmit location of the measurement circuit and subtracting a weighted version of the carrier signal at a receive location of the measurement circuit. One or more compensation impedances can be used such that the sidebands of the carrier signal are received with the carrier signal suppressed with respect to the receive location.

Abstract: A method of calibrating a thermal sensor device is provided. The method includes extracting an incremental voltage to temperature curve for a diode array from a first incremental voltage of the diode array at a first temperature. The diode array and a device under test (DUT) which includes a thermal sensor are heated. After heating the diode array, a first incremental temperature is determined from the incremental voltage to temperature curve for the diode array and a second incremental voltage of the diode array after heating the diode array. An incremental voltage to temperature curve is extracted for the DUT from the first incremental temperature, a first incremental voltage for the DUT at the first temperature, and a second incremental voltage of the DUT after heating the device under test. A temperature error for the thermal sensor is determined from the incremental voltage to temperature curve for the DUT.

Abstract: A test system, a method for manufacturing an electronic device, and a method for testing a wafer or electronic device that includes coupling a transistor in a series circuit with a capacitor and a resistor, coupling a voltage source to the capacitor to charge the capacitor to a non-zero DC voltage while the transistor is turned off, disconnecting the voltage source from the capacitor while the transistor is turned off, turning the transistor on while the voltage source is disconnected from the capacitor, measuring a voltage signal across the resistor while the transistor is turned on, and determining a test result indicating whether the transistor has an acceptable dynamic on-state resistance according to the voltage signal across the resistor.

Abstract: Sampling timings at a plurality of measurement points at which waveform data of a power line is sampled are easily synchronized to each other. A measurement device includes: a sampling unit configured to sample a waveform of at least one of a voltage and a current at a measurement point of a power line at a predetermined sampling timing; a processing unit configured to execute processing of the waveform sampled by the sampling unit; a time information acquisition unit configured to acquire time information from a time information provision device that is communicatively connected through a network; and an adjustment unit configured to adjust a processing timing of the processing on the basis of the time information acquired by the time information acquisition unit.

Abstract: A current sensing circuit includes a sensing resistor, a current monitor, a variable resistor, and a processor. The sensing resistor is disposed on a to-be-sensed circuit and coupled between first and second first voltage terminals of the to-be-sensed circuit. The current monitor includes first and second terminals. A first winding is coupled between the first terminal and the first voltage terminal, and a second winding is coupled between the second terminal and the second voltage terminal. The variable resistor is connected in series with the first winding between the first voltage terminal and the first terminal. The current monitor obtains a sensed current according to a first voltage on the first terminal, a second voltage on the second terminal, and an impedance of the sensing resistor and generates a sensing signal. The processor determines whether to adjust an impedance of the variable resistor according to the sensing signal.

Abstract: A wafer probe test system includes a chuck to support a wafer, and a probe card having a first side to face the chuck, an opposite second side, and an aperture that extends between the first and second sides. The system also includes a probe head mounted to the first side of the probe card and having probe pins to contact a device under test of the wafer, and an infra-red thermal sensor facing the aperture of the probe card to sense a temperature of the wafer.

Abstract: Some examples described herein provide for an on-die virtual probe in an integrated circuit structure for measurement of voltages. In an example, an integrated circuit comprises a voltage-controlled frequency oscillator circuitry and a processor circuitry. The voltage-controlled frequency oscillator circuitry comprises a plurality of circuitry components and is configured to generate a signal having a frequency related to a supply voltage. The voltage-controlled frequency oscillator circuitry is disposed at a location of the integrated circuit proximal to the supply voltage being monitored. The processor circuitry is configured to identify a relationship between the frequency of the signal and the supply voltage. The processor circuitry is also configured to determine a value of the supply voltage associated with the signal based on the identified relationship. The processor circuitry further monitors on-die transient voltages at the location of the integrated circuit based on the value of the supply voltage.

Abstract: A current sensor is disclosed. The current sensor is substantially immune to stray fields due to the position and orientation of at least two magnetic field sensors and their respective axes of maximum sensitivity, as well as a total current sensor output that is a based on a difference of the individual magnetic field sensor outputs. The specific position and orientation of the magnetic field sensors allows for the current sensor to be smaller than known sensors of similar sensitivity.

Abstract: Circuitry, systems, and methods for fault detection and reporting comprise a fault detection circuit configured to detect one or more fault conditions that cause a state change in a fault pin voltage representative of a transceiver failure. Once the state of the fault pin voltage changes, a transceiver input generates a fault detection code. In embodiments, in response to the transceiver input receiving a first signal, the fault detection code is shifted to a transceiver output that may communicate the fault detection code to a controller. Once the transceiver input receives a second signal, the fault pin voltage may be reset to clear the fault detection code before resuming operations, including detecting additional fault conditions as they arise.

Abstract: The present invention discloses a method for detecting open phase of a startup/standby transformer based on optical CT. A startup/standby transformer in a power plant is in a no-load condition for a long time as a standby power supply. Once a single-phase open phase fault occurs, there is no significant change in the voltage phasor and voltage sequence component of each side. If not found in time, the defect may pose a great threat to the safe operation of the power plant. In the present invention, the optical CT is used to detect a three-phase current of the high-voltage side of the startup/standby transformer. If the current satisfies an open phase criterion, it is determined that an open phase fault occurs, and then, an alarm signal is given after a delay and an operator is informed to handle the fault in time. Therefore, the operation reliability of the startup/standby transformer system in the power plant is enhanced.

Abstract: A transformer state evaluation method combining a FAHP method, a DEMATEL method, and a CRITIC method is provided and includes: selecting a plurality of groups of state quantities, building a hierarchical indicator system; calculating an influencing degree and an influenced degree by using the DEMATEL method on a subjective level, calculating a weight of each of a plurality of indicators of an indicator layer through the FAHP method and the DEMATEL method, calculating the weights of the indicators of the indicator layer through the CRITIC method on an objective level; calculating an optimal weight according to the indicator subjective weights and the indicator objective weights; and calculating state scores layer by layer, finally determining an actual health condition of each of a plurality of transformers by combining state level classification rules. In the disclosure, the weights are calculated based on the subjective level and the objective level.

Abstract: An electrical measurement apparatus may include a bias voltage generator configured to generate and output a bias voltage, a bias probe coupled to the output of bias voltage generator configured to apply voltage bias to a first portion of an external circuit which may be subjected to environmental stresses such as vibration, temperature, humidity etc., a measurement probe configured to receive a second electrical signal from a second portion of the external circuit, and a control unit configured to control the bias voltage generator to generate different bias voltages, patterns, AC/DC etc., receive the second electrical signal from the measurement probe and cause the device to output a response in the second electrical signal to the time-domain discontinuity in the first electrical signal.

Abstract: A method of testing semiconductor devices includes placing a plurality of semiconductor devices in a carrier assembly and performing at least one testing operation on the plurality of semiconductor devices while they remain inside the carrier assembly.

Abstract: A semiconductor device includes a voltage comparison circuit and a calibration control circuit. The voltage comparison circuit compares test reference voltages and generates a comparison result signal. The calibration control circuit controls an offset value of the voltage comparison circuit.

Abstract: The present invention relates to a sensor suite comprising at least one sensor. More particularly, the present invention relates to a sensor suite for measuring absolute and/or relative position, location and orientation of an object on or in which the sensor suite is employed. The present invention further relates to improved, novel sensor types for use in the sensor suite. More particularly, the present invention relates to an improved, novel magnetometer that is self-calibrating and scalable. Still more particularly, the present invention relates to such a magnetometer that is miniaturized. Further embodiments of the present invention relate to systems and methods for providing location and guidance, and more particularly for providing location and guidance in environments where global position systems (GPS) are unavailable or unreliable (GPS denied and/or degraded environments).

Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of an electrode pad of a TEG to facilitate the evaluation of electrical characteristics. According to the present invention, the above described problem can be solved by arranging a plurality of probes in a fan shape or manufacturing the probes with micro electro mechanical systems (MEMS) technology.