Abstract: A semiconductor package test system includes a test pack on which a semiconductor package is loaded, and a semiconductor package testing apparatus. The semiconductor package testing apparatus includes a receiving section that receives the test pack. The receiving section includes a pack receiving slot into which the test pack is inserted. The test pack includes a chuck on which the semiconductor package is fixed, a probe block disposed above the chuck, and a connection terminal. The receiving section includes a receiving terminal that is electrically connected to the connection terminal when the receiving terminal contacts the connection terminal. The probe block includes at least one needle configured to be electrically connected to the semiconductor package disposed on the chuck upon the chuck moving toward the semiconductor package. The receiving section is provided in plural.

Abstract: A probe card includes a sub-board, having a heating layer, connected to a probe pin. A main board is connected to the sub-board and includes a first output terminal configured to output first power received from a first power supply to the heating layer in a first mode. A power converter is configured to lower a first voltage corresponding to residual power received from the first power supply to a second voltage and output the residual power in a second mode. A second output terminal is configured to receive the residual power from the power converter and second power from a second power supply and output third power including the residual power and the second power to a device under test in the second mode. A first switch unit is connected to the first power supply, the first output terminal, and the power converter.

Abstract: A semiconductor device test apparatus for improving a loss rate of a test signal in testing a device under test is provided. The semiconductor device test apparatus includes a probe interface board, a pogo block disposed on the probe interface board and electrically connected to a device under test, an equipment board disposed under the probe interface board, an alternating current (AC) controller, transferring and receiving an AC signal for performing an AC test on at least one of the device under test and the pogo block, being mounted on the equipment board, and a physical layer equalizing (PLE) board disposed between the probe interface board and the equipment board, a first equalizing circuit, decreasing loss of the AC signal, being mounted on the PLE board.

Abstract: The present invention provides a multi ground line disconnection inspection device as a device for inspecting whether a plurality of ground lines that are connected to a ground node of an electronic control device are disconnected, including a plurality of test lines having one end connected to a plurality of ground lines, respectively, a plurality of connection switches connected to the ground node and the other end of a plurality of test lines, respectively, a plurality of test power supplies for applying test voltages to a plurality of test nodes respectively positioned on a plurality of test lines, respectively, and a determination unit for determining whether a plurality of ground lines are disconnected by detecting voltages of a plurality of test nodes.

Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.

Abstract: A system includes a platform and a contactor. The platform has a side configured to support a frame with a carrier structure and electronic devices each having first and second sides and a terminal, the first side positioned on the carrier structure, and the terminal exposed in a first portion of the second side. The contactor has first and second sides, a contact and a heater. The contact is exposed on the first side of the contactor to contact the terminal in a first portion of the second side of a selected one of the electronic devices, and the heater is exposed on the first side of the contactor to apply heat to a second portion of the second side of the selected one of the electronic devices.

Abstract: The present disclosure relates to a detection circuit for detecting oscillations of a regulated supply signal. The detection circuit includes a filter circuit to filter the regulated supply signal in order to obtain a filtered supply signal. A peak value detector circuit is designed to detect an extremum of the filtered supply signal. A comparator circuit is designed to compare the detected extreme value with a threshold value and to indicate an understepping or exceedance of the threshold value.

Abstract: An electronic component handling apparatus handles a DUT and includes: an acquiring device that acquires current three-dimensional shape data of a DUT container having a plurality of accommodating portions each capable of accommodating the DUT; and a computer device that: calculates a first correction amount from the current three-dimensional shape data and corrects the current three-dimensional shape data based on the first correction amount; extracts, from the corrected three-dimensional shape data, at least one of a height and a slope of each of predetermined regions of the DUT container; and determines an accommodation state of the DUT based on an extraction result. The first correction amount represents at least one of a movement amount and a rotation amount in a planar direction of the current three-dimensional shape data with respect to an initial state of the DUT container set in advance.

Abstract: A system comprises first and second Hall-effect sensors and an amplifier. The first Hall-effect sensor has a first bias current direction parallel to a first direction, a pair of first bias input terminals spaced along the first direction, and a pair of first sense output terminals spaced along an orthogonal second direction. The second Hall-effect sensor has a second bias current direction parallel to the second direction, a pair of second bias input terminals spaced along the second direction, and a pair of second sense output terminals connected out of phase with the first sense terminals. The amplifier has a pair of amplifier input terminals coupled to the first and second sense terminals.

Abstract: The present invention discloses an AC impedance measurement circuit with a calibration function, which is characterized in that only one calibration impedance is needed, associated with a switch circuit. Based on the measurement results of the two calibration modes, an equivalent impedance of the switch circuit, circuit gain and phase offset can be calculated. Based on the above results, the equivalent impedance of the internal circuit is deducted from the measurement result of the measurement mode to accurately calculate an AC conductance and a phase of the AC conductance for impedance to be measured. In addition, by adjusting a phase difference between an input sine wave signal and a sampling clock signal, impedance of the same phase and impedance of the quadrature phase can be obtained, respectively, and the AC impedance and phase angle of the impedance to be measured can be calculated.

Abstract: A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

Abstract: Semiconductor devices that include test circuitry to measure internal signal wire propagation delays during memory access operations, and circuity configured to store delay information that is used to configure internal delays based on the measured internal signal propagation circuit delays. The semiconductor device includes a test circuit configured to measure a signal propagation delay between a command decoder and a bank logic circuit based on time between receipt of a test command signal directly from the command decoder and a time of receipt of the test command signal routed through the bank logic circuit.

Abstract: A wafer inspection system is provided. The wafer inspection system comprises: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.

Abstract: Herein disclosed are a wafer, a wafer testing system, and a method thereof. Said wafer testing method comprises the following steps. First, an incident light is provided toward a wafer. And, a wafer surface image corresponded to the wafer is generated. Then, determining whether the wafer surface image has a plurality of first strips and a plurality of second strips, and the plurality of first strips and the plurality of second strips are symmetrical. When the wafer surface image has the plurality of first strips and the plurality of second strips, and the plurality of first strips and the plurality of second strips are symmetrical, a qualified signal corresponded to the wafer is provided.

Abstract: Described here are systems and methods for mitigating or otherwise removing the effects of short-term magnetic field instabilities caused by oscillations of the cold head in a cryogen-free magnet system used for magnetic resonance systems, such as magnetic resonance imaging (“MRI”) systems, nuclear magnetic resonance (“NMR”) systems, or the like.

Abstract: A board-like connector, a dual-ring bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-ring bridges spaced apart from each other and an insulating layer. Each of the dual-ring bridges includes two carrying rings, two cantilevers respectively extending from and being coplanar with the two carrying rings, two abutting columns respectively extending from the two cantilevers along two opposite directions, and a bridging segment that connects the two carrying rings. The insulating layer connects the two carrying rings of the dual-ring bridges, and the two abutting columns of the dual-ring bridges respectively protrude from two opposite sides of the insulating layer. The two abutting columns of each of the dual-ring bridges are configured to be respectively abutted against two boards.

Abstract: A system includes a signal generator, configured to pass a generated signal, which has two different generated frequencies, through a circuit including an intrabody electrode. The system further includes a processor, configured to identify, while the generated signal is passed through the circuit, a derived frequency, which is derived from the generated frequencies, on the circuit, and to generate, in response to identifying the derived frequency, an output indicating a flaw in the electrode. Other embodiments are also described.

Abstract: A system for distribution transformer monitoring may comprise a distribution transformer that includes a transformer fluid tank, a monitoring unit that includes a plurality of sensors, wherein the monitoring unit is coupled to the distribution transformer, and wherein the plurality of sensors comprises a fluid sensor that includes a sensor probe that extends out of the monitoring unit into the transformer fluid tank of the distribution transformer, and a communication unit coupled to the distribution transformer and communicatively coupled to the monitoring unit. The monitoring unit may further comprises a sensor module to receive sensor data from the plurality of sensors, a storage module to store the sensor data in an internal data storage device of the monitoring unit, an analysis module to analyze the sensor data to determine generated data, and a communication module to communicate the sensor data or the generated data to a remote computing device.

Abstract: A current sensor includes a battery terminal portion that is conductive and is fastened to a battery post; a shunt resistor for current detection, which is formed in a plate shape and is electrically connected to the battery terminal portion; and a circuit board that is formed in a plate shape and is electrically connected to the shunt resistor, in which the shunt resistor is erected on a main surface of the circuit board. With this configuration, since the shunt resistor and the circuit board can be arranged so as not to face each other and not confront each other, the influence of heat generated by the shunt resistor can be suppressed.

Abstract: A low-noise current sensor enables large dynamic range current measurements of alternating and direct current flows. The current sensor includes a first substrate, a first conductor, a magnetic flux conductor comprising a first portion orthogonal to the first conductor and a second portion, the second portion penetrating the first substrate, an inductive sensor comprising a first plurality of loops around the second portion of the magnetic flux conductor on the first substrate, wherein the first plurality of loops is orthogonal to the second portion of the magnetic flux conductor, and a Faraday cage that encloses the first plurality of loops and separates the first plurality of loops from the first conductor.