Abstract: An improved user computer interface visual display workstation (UCIVDWS) system and an improved method for carrying out the system that concerns a common, password controlled UCIVDWS of the system for selectively controlling and monitoring one or more computer site arrangements; with each computer site being controllable in multi-mission fashion whether any computer site arrangement is arranged locally to or remote from the workstation arrangement; and even if any computer site arrangement has a different operating system from either any other system computer site arrangement or the system workstation itself. Moreover, the visual display at the workstation is generally made up of a multi-section, multi-formatted configuration such that certain sections of the workstation display have a plurality of user selectable function button.

Abstract: A method is provided for configuring an automated media dispense machine (115). A graphical display image representing a template for generating a configuration of dispensing parameters for the dispense machine (115) is presented on a display device (151). A graphic manipulation tool (137) is provided for graphically adjusting the display image. The display image is modified using the graphic manipulation tool (137) to configure the dispensing parameters for the dispense machine (115). A configuration of dispensing parameters for the dispense machine (115) is generated based on modifications to the display image.

Abstract: A graphical editing system is provided which creates a "place-holder" that holds or suspends a complex gesture or complex menu selection before committing to the command. Such a place-holder acts as a virtual stylus, i.e. as if the user was actually holding the stylus to the screen just prior to committing to the command. The virtual stylus thus allows the user to execute other arbitrary drawings or menu commands or gestures while the original complex command is suspended. The user can then return to the complex command he/she chooses and remove the place-holder to commit to the command or cancel the command if desired. The virtual stylus can take on many forms, e.g., a hand with a pointed finger, an icon or any other desired indicator, and the virtual stylus can be created by any user action, e.g., an actuated stylus button, pressure sensitive display surface or by sensing the time during which the stylus remains stationary on the display screen. The virtual stylus can be removed in basically the same way.

Abstract: A method and system for facilitating the selection of icons. Those icons which are next likely to be used are selected and automatically moved towards a cursor thereby facilitating selection of the icons. Additionally, those icons likely to be used or other icons selected by a user may track the cursor such that those icons are always close to the cursor and capable of being easily selected. Further, in order to facilitate selection of icons, icons are provided with the capability of announcing themselves when a cursor comes close to the icon. In addition, it is possible to reduce the amount of clutter on a computer display so that icons may be easily selected. In order to clean up a computer display, icons which are least likely to be used are faded, eliminated or shrunk to a smaller size. In another embodiment, icons that are not used very often may disappear into a master icon and further, icons which have a conceptual relationship between them may be linked by a visual graphical representation.

Abstract: A frame buffer cache is arranged to store part of image data in an image memory so that a CPU and a drawing processor can perform image data read/write operations by only accessing the frame buffer cache. Therefore, the image data read/write operations of the CPU and the drawing processor can be performed simultaneously with the access to a dual port image memory, thus improving the drawing performance of the CPU and the drawing processor.

Abstract: An apparatus and method for storing pixel data in a video memory having a plurality of slices increases the performance of line drawing by ensuring that for a given pixel, neighboring pixels in neighboring scan lines are stored in separate slices of video memory. One embodiment of the invention includes the step of appending a number of offset bits to the end of each scan line, where the number of offset bits is less than the total number of bits contained in the plurality of slices. Another embodiment of the invention rearranges the pixels of every other scan line. Another embodiment adds an offset number of pixels which is equal to the number of pixels per slice times the number of slices, then alternates ordered pixels with rearranged pixels throughout successive scan lines. Performance is further increased by providing a plurality of memory controllers corresponding to the plurality of slices of memory which may operate asynchronously to interleave memory access commands.

Abstract: A graphics processor enhancement system having a processor connected through data and lower address lines to two areas of random access memory (RAM). One area of RAM stores an image frame and the other area of RAM stores a copy of a background section of the image frame. The processor is connected through a read/write line and higher address lines to a programmable logic device (PLD), the output of which functions to enable one of the two areas of RAM. The system also stores a transparent memory map containing a copy of the object surrounded by transparent pixel values. The processor provides an animated display by modifying a portion of the image frame, such that an object stored therein is incremental moved across the image frame. The PLD enables the processor to read the copied background section, overlay this background section with the transparent memory map and write the resulting combination to the image frame over the old object stored therein.

Abstract: A parallel processing system for processing data matrices, such as images, is disclosed. The system includes a plurality of processing units, organized in four blocks of eight processing units per processing chip, and external cache burst memory, wherein each processing unit is associated with at least one column of the external memory. A barrel shifter connected between the memory and the processing units allows data to be shifted to adjacent processing chips, thus providing the means for connecting several of the chips into a ring structure. Further, digital delay lines are connected between the barrel shifter and the processing units, thus providing the capability of delaying, via a predetermined number of clock cycles, incoming column data. Each processing unit is provided with a nine bit cache memory.

Abstract: A method and apparatus for transmitting print data signals serially to a printing device is disclosed. Print data for printing dots selectively line by line is stored as a plurality of bytes in which each byte represents the number of contiguous binary bits to be output to the printing device having the same binary value. The bytes are output to a comparator which receives the output of a counter driven by clock signals. The counter is started when a byte is output and the clock signals clock a data line held at a level representing the value of the bits. When the count equals the byte, the comparator toggles the data line so that it is at a level representing the next binary bits to be output. The apparatus is disclosed for use in a franking machine.

Abstract: A memory subsystem for use between a CPU and a graphics controller in a typical small computer system has a cache interface for the CPU and a FIFO interface for the graphics controller. This configuration optimizes the data transfers for both the CPU and the graphics controller, and allows both to operate in a manner generally asynchronous to each other. This caching FIFO provides enhanced performance by matching the interface to the unique data requirements of the devices accessing the data within the caching FIFO. For the CPU, the caching FIFO appears as a normal data cache. For the graphics controller, the caching FIFO appears as a normal dual port FIFO, which optimizes the highly sequential data transfers characteristic of graphics controllers. The simple design of the caching FIFO provides maximum performance for a minimum of gates, making the circuit well-suited to efficient implementation in silicon.

Abstract: A method, system and program for navigating within any compound graphical object in a graphical user interface presented on a display. The compound graphical object has an arbitrary number of hierarchically ranked levels. First, the system determines whether a command to move within the compound object was issued from a pointing device or from a keyboard device. If issued from a pointing device, a lowest level object in the compound object is found which encompasses a hot spot of a pointer icon controlled by the pointing device. The level to which the lowest level object belongs is made active. If the selection command was issued from a keyboard device, a next object in the compound object is selected, the next object being established by the keyboard user command and other information such as the relative hierarchical and spatial positions of the current and next objects.

Abstract: Image data is hierarchically coded by a coder, and the coded data is stored in a database. A decoder hierarchically decodes the coded data stored in the database, and image data corresponding to each hierarchy is generated. The decoder generates image data of a plurality of levels of resolutions from a low resolution to high resolution from the coded data stored in the database. The image data of the high resolution is original image data. Editing such as enlargement, reduction, transfer, and rotation, specified by an operator, is executed using the image data of the low resolution obtained from the decoder. The content of the edit processing by the operator is stored in a memory. When the editing operation ends, CPU executes the edit processing on the original image data obtained from the decoder based on the content of the edit processing stored in the memory. The final editing is thus performed on the original image data.

Abstract: In a computer graphics system, a semiconductor chip used in performing texture mapping. Textures are input to the semiconductor chip. These textures are stored in a main memory. Cache memory is used to accelerate the reading and writing of texels. A memory controller controls the data transfers between the main memory and the cache memory. Also included within the same semiconductor chip is an interpolator. The interpolator produces an output texel by interpolating from textures stored in memory. The interpolated texel value is output by the semiconductor chip, thereby minimizing transmission bandwidth as well as redundant storage of texture maps in a multi-processor environment.

Abstract: A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.

Abstract: Raster display memories are often arranged to output groups of pixels in progressive blocks, each having a plurality of pixels and each pixel having a plurality of fields. The fields in each pixel may provide color, overlay and cursor information for an individual position on a video screen. The numbers of bits in each pixel and in each field may be variable in different applications. In this system, control information indicates the starting position of each block, the location of each pixel in each block and each field in each pixel and the width of each pixel and each field in number of bits. Using this control information, the system recovers the pixels in each block and the fields in each pixel and processes such information to provide a display of the pixel information on a video screen. The number of bits contained in each field may be expanded to a width (e.g. 8) when the field width is less than eight (8) bits.

Abstract: A portable computer that includes a first ROM for storing an OS, a second ROM for storing at least one piece of existing application software, and a flat display panel for displaying at least one icon to read out the existing application software stored in the second ROM. Since the DOS and the application program are respectively stored in a DOS ROM and an application ROM, the DOS or the application can be quickly executed without install processing from floppy disks.

Abstract: An image filing method, in which a plurality of images are registered one by one, and the registered images are retrieved by adding a retrieval condition so as to be simple and not require time and labor at the registration and retrieval times. A plurality of symbols for featuring objects in the images are set in advance, and the images are registered corresponding to the selected symbols. At the image retrieval time, the symbols are selected, and the images corresponding to the selected symbols are read out.

Abstract: Pixel data is selected from among first and second dynamic-image memories (DI1, DI2) and a static-memory (SI). In the invention, (a) first and second window area memories (WA1, WA2) for designating shapes and sizes of windows to which video dynamic-images are assigned respectively, (b) first and second dynamic-image area memories (DA1, DA2) for designating memory locations of data stored in both the dynamic-image memories, and (c) a priority control register for designating which video dynamic-image should be displayed in front when video dynamic-images overlap with each other are provided, whereby display for every pixel is executed according to a logical AND value of read-out data from WA1 and read-out data from DA1, a logical AND value of read-out data from WA2 and read-out data from DA2, and read-out data from the priority control register.

Abstract: Using the character processing method having a plurality of processing schemes, character patterns are outputted in a plurality of windows using any of the processing schemes. The requirements of each window are discriminated, a processing scheme suited to a particular window is selected from the plurality of processing schemes in response to the requirements, and a character or graphic processed by the processing scheme selected for the window is outputted for each and every window.

Abstract: A system for storing and processing an array of data-elements formatted as a plurality of pages of the data elements, and especially for use in a demand-paged dual memory system, comprises a memory in which each memory location has a capacity of, for example, 32 bits and a processing means for processing data elements and reading the data elements from and/or writing them to the memory. In order to enable full use to be made of the memory and to facilitate the use of demand-paging when dealing with data-elements having less bits, for example 16 or 8 bits, a plurality of such data-elements are stored at different bit levels in each memory location so that at no memory location is there stored data-elements from more than one page.