Abstract: The present invention provides an architecture for a core logic unit including an embedded graphics controller. This architecture facilitates high-bandwidth communications between the graphics controller and other computer system components, such as the processor and the system memory. Thus, one embodiment of the present invention provides a core logic unit within a computer system including a processor interface for communicating with a processor, a memory interface for communicating with a system memory, and a bus interface for communicating across a computer system bus. It also includes a switch, coupled to the processor interface, the memory interface and the bus interface, for facilitating data transfers between these interfaces. The switch is connected to a graphics controller, which is located on the same semiconductor chip as the switch, for performing computations for displaying images on a computer system display.

Abstract: To allow the user who wants to use three-dimensional virtual reality spaces to easily select a desired three-dimensional virtual reality space. When the browser is started with data about a three-dimensional virtual reality space stored in a predetermined directory, this predetermined directory is searched. According to the search result, an entry room in which three-dimensional icons representing three-dimensional virtual reality spaces are arranged is generated and displayed. The three-dimensional icons arranged in the entry room are linked to the data of the corresponding three-dimensional virtual reality spaces. When user clicks on a desired three-dimensional icon, the corresponding three-dimensional virtual reality space is displayed.

Abstract: A graphics display command list handler and method requests allocation of memory, such as system memory, in the form of a circular FIFO which stores the display command list as a memory display list (MDL), such as a host memory display list. A processor, such as a graphics processor, communicates a host memory display list read pointer to the host processor to facilitate display list signaling by the graphics processor. The host processor (or other processor) maintains a write pointer which points to a last host memory entry in the display list. The read pointer is maintained by the graphics processor and written back to the host processor.

Abstract: A clear color and count are stored in a frame buffer controller and in a video controller. The image buffer is cleared by writing the clear color into a color bit field and the count into a count bit field of each pixel. For each frame drawn, the count bit field of each pixel modified is updated with the count stored in the frame buffer controller. The counts stored in the frame buffer controller and the video controller are incremented with each new frame. When the counts reach maximum, the process repeats. Each time a pixel is read, the pixel's color bit field is replaced with the stored clear color if the pixel's count bit field is not equal to the stored count. The color bit field and the count bit field may be part of the same word of frame buffer memory. Or, the count value may be stored in an alpha bit field in lieu of an alpha value.

Abstract: A method of buffering graphics vertex commands adaptively. A minimally-formatted vertex values buffer is created. As vertex commands are received from application software, attribute values are stored in an attribute values buffer until a vertex coordinate command is received. Upon receipt of a vertex coordinate command, attribute values are copied from the attribute values buffer into the vertex values buffer. Whenever application software issues a vertex attribute command corresponding to an attribute type that is not currently reflected in the vertex values buffer format, the vertex values buffer is automatically reformatted to include the new attribute type. Thus, the vertex values buffer automatically adapts itself to the behavior of the application. Multiple primitives are buffered between flushes. First-call and subsequent-call versions of code are provided for vertex commands. At initialization, a dispatch table is populated with pointers to the first-call versions.

Abstract: Image data (derived from film or video clips) is transferred from storage to high speed memory. After a transfer has taken place, a prediction is made as to subsequent image frames that will need to be transferred. The predicted images are transferred from storage to high speed memory while previously transferred data held in memory is processed.

Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory is generated from the CPU, the memory controller holds it once, requests the display controller to stop the access to the memory which is in execution, when data to the access executed already is transferred from the memory, holds it, and transfers the access request from the CPU bus which is held by the memory. When the access from the CPU bus ends, the memory controller restarts the access stopped in the display controller and passes the held data to the display controller.

Abstract: A method an system provide that image processing operations and graphics processing are both performed by a graphics rendering system. The texture memory and a texture filter of the graphics rendering system are used to perform look-up table operations as well as multiply and accumulate operations typically associated with image processing.

Abstract: The present invention is a system and method for controlling information displayed on a first processor-based system, from a second processor-based system. The apparatus comprises a memory to store instruction sequences by which the second processor-based system is processed, and a processor coupled to the memory. The stored instruction sequences cause the processor to: (a) examine, at a predetermined interval, a location of a currently displayed image; (b) compare the location with a corresponding location of a previously displayed image to determine if the previously displayed image has changed; (c) transmitting location information representing the change; and (d) storing the changed information on the first processor-based system. Various embodiments are described.

Abstract: A method and apparatus for synchronizing the execution of a sequence of graphics pipelines is provided. For a representative embodiment a sequence of graphics pipelines are connected in a daisy-chain sequence. Each pipeline operation can be controlled to operated in one of two modes. The first is a local mode where the pipeline outputs its own digital video data. The second is a pass-through mode where the pipeline outputs digital video data received from preceding graphics pipelines. The pipelines are configured to allow an application executing on a host process to select the next pipeline that will enter local mode operation. The pipeline that is selected to enter local mode operation asserts a local ready signal when it is ready to begin outputting its digital video information. Each of the pipelines monitors the state of a global ready signal. When the global ready signal becomes asserted it means that the pipeline that is selected to enter local mode operation is ready.

Abstract: To accelerate drawing input processing, a plurality of drawing pipelines 20 are provided and each drawing pipeline comprises a queue 21, a density data generator 23, a multiplier 24, an accumulator 25, and a cache 26. A stroke is divided, for example, into four, and allocated to each drawing pipeline 20. By each drawing pipeline 20, a next pixel is processed after a former pixel is processed for a plurality of patches according to the scan order.

Abstract: A graphics processing device includes a variable performance setup engine that processes vertexes of polygons to create surface coefficients, and a rasterizer that processes the surface coefficients to create pixel values corresponding to each pixel location within each polygon. The variable performance setup engine is structured so as to provide the surface attributes of each polygon within a time that is correlated to the size of the polygon. In this manner, the overall polygon processing rate will be substantially related to the size of the polygon. By providing a short processing time for small polygons, and a longer processing time for larger polygons, the image processing rate is shown to be less dependent upon the sizes of the polygons that comprise the image. The invention thereby provides for an overall image processing rate that is substantially independent of the complexity of the image being rendered.

Abstract: The present invention provides a graphics memory system of a computer graphics display system which utilizes a batching architecture in conjunction with detached Z buffering for minimizing paging overhead. The graphics memory system comprises a memory controller which receives a batch of pixels from a host CPU of the computer graphics display system when a 3D rendering mode is in effect. Each pixel has a pixel color and corresponding Z coordinate associated with it. The memory controller then performs a Z comparison test wherein Z coordinates of the batch are compared with existing Z coordinates read out of a frame buffer memory to determine whether or not each new color of the batch associated with the Z coordinate being compared should be written into the frame buffer memory. If the results of a Z comparison test pass, the new pixel color and Z coordinate are queued for writing into the frame buffer memory.

Abstract: A graphics request stream is transferred from a host processor to a graphics card via a host bus so that the stream traverses the host bus no more than once. To that end, the graphics card has a graphics card memory, and the host processor has a host memory configured in a first memory configuration. The graphics card memory may be configured in the first memory configuration, and the graphics request stream is received directly in a message from the host processor (via the host bus). Upon receipt by the graphics card, the graphics request stream is written to the graphics card memory.

Abstract: An apparatus and method for processing ultrasound data is provided. The apparatus includes an interface operatively connected to a memory, a programmable single instruction multiple data processor (or two symmetric processors), a source of acoustic data (such as a data bus) and a system bus. The memory stores data from the processor, ultrasound data from the source, and data from the system bus. The processor has direct access to the memory. Alternatively, the system bus has direct access to the memory. The interface device translates logically addressed ultrasound data to physically addressed ultrasound data for storage in a memory. The translation is the same for data from both the processor and the source for at least a portion of a range of addresses. The memory stores both ultrasound data and various of: beamformer control data, instruction data for the processor, display text plane information, control plane data, and a table of memory addresses. One peripheral connects to the ultrasound apparatus.

Abstract: A video memory handling system and method for providing a graphic computer-implemented process with a predetermined amount of video memory to be used by the graphic process to perform a predetermined graphic-related operation within a set-top box environment. A first video memory portion is provided which has an allocation status with respect to the graphic process. A video memory handling data structure indicates the allocation status of the first video memory portion. A video memory manager which is connected to the video memory handling data structure reallocates the first video memory portion based upon the video memory handling data structure. The reallocated first video memory portion is utilized by the graphic process to perform the predetermined graphic-related operation.

Abstract: Distinct full motion video segments may be reproduced on a plurality of playback platforms by storing duplicate video segments on each of a plurality of direct access storage devices. In response to a request for a video segment, a direct access storage device for retrieval of the video segment is selected from among devices listed in a drive information table. The selected direct access storage device is then instructed to retrieve the video segment. Finally, the drive information table is updated to reflect use of the selected direct access storage device for retrieval.

Abstract: On the basis of control information of an image received from an external device via an external parallel interface, a frame memory control unit stores image data, which has been transferred from the external device, in a band memory B obtained by partitioning a frame memory into band memories A and B. The frame memory control unit subjects the image stored in the band memory B to image processing based upon the received control information, stores the processed results in the band memory A and then sends image data, which is obtained by image-processing the stored results, to a printer or to the external device. Accordingly, highly sophisticated image processing can be achieved with a minimal memory capacity.

Abstract: The present invention relates to a display memory control apparatus which can shorten a waiting time in making an access to a VRAM from a CPU without making large a circuit scale and causing an increase of power consumption. A data width of a VRAM is previously set to plural times as much as a data bus width of a CPU. A write data from the CPU is temporarily stored in a pre-buffer, and is transferred to one of data buffers included in a write buffer. The data buffer is specified by a low-order address. A VRAM control circuit can write all data or data of arbitrary combinations from data buffers into an address of VRAM specified by a high-order address buffer by one-time access.

Abstract: A graphics accelerator including an address remapping memory which straddles slow address spaces and fast address spaces.