Abstract: An apparatus and method for processing ultrasound data is provided. The apparatus includes an interface operatively connected to a memory, a programmable single instruction multiple data processor (or two symmetric processors), a source of acoustic data (such as a data bus) and a system bus. The memory stores data from the processor, ultrasound data from the source, and data from the system bus. The processor has direct access to the memory. Alternatively, the system bus has direct access to the memory. The interface device translates logically addressed ultrasound data to physically addressed ultrasound data for storage in a memory. The translation is the same for data from both the processor and the source for at least a portion of a range of addresses. The memory stores both ultrasound data and various of: beamformer control data, instruction data for the processor display text plane information, control plane data and a table of memory addresses. One peripheral connects to the ultrasound apparatus.

Abstract: A graphics processor includes a plurality of interrelated functional modules and at least one register associated with each of the functional modules. The plurality of interrelated functional modules are interconnected by a data pipeline for conveying data, and each register is configured to control a function of its associated functional module. The graphics processor also includes a control bus interconnecting each of the registers for conveying instructions, and an instruction controller for decoding instructions for use with the graphics processor. The control bus and the data pipeline are physically separate, and the instruction controller includes a register setting unit adapted to set the registers via the control bus in accordance with a decoded instruction. This enables the function of each of the functional modules to be configured in response to each instruction.

Abstract: An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and to mix indexed and direct vertex values and attributes; a projection matrix value set command; a display list call object command; and an embedded frame buffer clear/set command.

Abstract: Incoming geometry data are buffered in one or more buffers. The data are written to the buffers in an order which is not necessarily the order in which a processor or processors that construct images from the data need the data for fast processing. The data are provided to the processors in the order needed for fast processing. In some embodiments, fast processing involves starting critical path computations early. Examples of critical path computations are lighting computations which take more time than position computations. At least one processor has a pipelined instruction execution unit. The processor executes critical path computation instructions as long as a critical path instruction can be started without causing a pipeline stall. When no critical path instructions can be started without causing a stall, the processor starts a non-critical path instruction.

Abstract: A method and apparatus for processing data with improved concurrency that begins when a host processor an application identifies a memory block of a plurality of memory blocks based on memory block status. The application then provides a data block to the memory block. The data block includes data for processing, which includes application data and operating instructions, and a memory block status update command. A data retrieval command and a sequential updating command are provided to a processing entity by the application. The processing entity then retrieves the data block in accordance with the data retrieval command and processes the memory block status update command to produce an updated memory block status. Finally, the processing entity provides the updated memory block status to the application in accordance with the sequential updating command.

Abstract: In a graphic processor, a rendering control circuit carries out weighted averaging on pieces of pixel data of source image information arranged to form a pixel-data matrix corresponding to a pixel matrix with columns of the pixel-data matrix being oriented perpendicularly to a scanning direction in order to compute a weighted average of pieces of pixel data on rows of the pixel-data matrix adjacent to each other and on a column of the pixel-data matrix perpendicular to the scanning direction in so-called blend processing. It is thus possible to eliminate a difference in image information between adjacent scanning lines, which is big in some cases. In this case, the rendering control circuit reads out pieces of pixel data from the pixel-data matrix sequentially in a direction perpendicular to the scanning direction and computes a weighted average of the pieces of data.

Abstract: An image processing apparatus is composed of a plurality of function processing units for performing image processing, a high priority function selection part for selecting functions, execution of each of which is required by a corresponding one of the function processing units, based on the predetermined priority for each of the functions; and a data control unit including a data transfer part for preferentially accessing the shared memory which the function selected by the high priority function selection part requires, and a plurality of data holding parts, each of the data holding parts holding a predetermined amount of data transmitted with each of the plurality of function processing units, wherein the data transfer part controls the bus connecting the CPU and the shared memory based on requirement sent from each of the function processing units, and each of the plurality of function processing units transmits data with the data control unit separately from the others of the plurality of function proces

Abstract: Herein disclosed is an electronic information distributing terminal equipment for storing and distributing the electronic information containing a text information and a corresponding motion image information in a memory card equipped with an electrically reloadable nonvolatile semiconductor memory device, which equipment comprises a card stock having a plurality of memory cards stored in advance with the information which has been transmitted through a communication interface for transmitting the electronic information to be distributed, wherein the electronic information is distributed by discharging the memory card even in response to a demand for distributing only the electronic information, and wherein the memory card inserted with the demand is utilized again as a new card stock.

Abstract: A method and apparatus employing lookup tables in a time sequential manner. A substrate has a display, a digital to analog converter, and a lookup table (LUT) formed thereon. The LUT is loaded with a LUT data set corresponding to an image subframe to be driven to the display. Successive LUT data sets corresponding to the next subframe are loaded after each subframe is driven to the display.

Abstract: A display device is disclosed that includes a cache memory consisting of memory segments, each memory segment being capable of storing an image fragment. A video generator is driven by a video cache reader, which builds up a screen image from complete or partial image fragments stored in the memory segments. By means of hardware counters and registers the address of an image point in the cache memory is derived from the address of the image point read in last. As a result of this, the screen image can be built up very rapidly, so that no special screen memory is required and the amount of data to be transferred is reduced.

Abstract: In an image display device, a ROM contains a plurality of image data indicative of the actions of an animal character. A RAM includes a plurality of action level registers each stores for each of which image data the state of inputs given to select and display the image data. The user gives a command corresponding to a respective image of an animal character to select and display the action of the animal character optionally. When a random number corresponding to the command is generated, image data which does not correspond to the input command can be displayed. If the generated random number has a particular value, the value of an action level register for the image data corresponding to the command is updated. Such operation is iterated and thus the value of the action level register is updated.

Abstract: A method and apparatus are disclosed for achieving improved mipmapped texture mapping performance in computer graphics systems. Page residence indicators obviate the need for address comparisons during texel accessing. A mipmap page number is generated for texture data of interest. A page residence bit is then selected responsive to the mipmap page number. If the page residence bit is in a first state, then the texture data is retrieved from a memory located within the graphics subsystem; but if the page residence bit is in a second state, then the texture data is retrieved from system memory. System-wide texture offset addressing obviates the constraints associated with fixed relative addressing schemes.

Abstract: Graphics call sequence optimizer for use in a graphics system that includes a display list memory to store graphics calls to be executed. The optimizer optimizes an original graphics call sequence that includes a plurality of graphics primitive data sets generated by a graphics application program in accordance with a graphics application program interface, such as OpenGL, generating an optimized graphics call sequence to be stored in the display list memory. The optimizer is configured to optimize the original graphics call sequence to produce the optimized graphics call sequence without storing the original graphics call sequence in the display list memory. In one embodiment, the optimizer is configured to coalesce graphics primitive data sets within the original graphics call sequence to generate a corresponding single graphics primitive data set in the optimized graphics call sequence that causes a same rendering in the graphics system as the original graphics call sequence.

Abstract: A method and apparatus for implementing a dynamic display memory is provided. A memory control hub suitable for interposition between a central processor and a memory includes a graphics memory control component. The graphics memory control component determines whether operands accessed by the central processor are graphics operands. If so, the graphics memory control component transforms the virtual address supplied by the central processor to a system address suitable for use in locating the graphics operand in the memory. In one embodiment, the graphics control component maintains a graphics translation table in the memory and utilizes the graphics translation table in transforming virtual addresses to system addresses. Furthermore, in one embodiment, the graphics control component reorders the addresses of the graphics operands to optimize for performance memory accesses by a graphics device.

Abstract: Picture data read out from a VRAM 18 are sent via line buffers 75a to 75d to a selection synthesis unit 63. The line buffer 75d receives picture data supplied from outside for sending the received picture data to the VRAM 18. The VRAM 18 can write the picture data from outside supplied via the line buffer 75d and read out the picture data based on addresses from a controller in the same way as other picture data. On the other hand, cache memories 74a and 74b can read out picture data under control by the controller 71 to display plural pictures in a tiled pattern on a display screen.

Abstract: An information processing apparatus secures a wide band width in a graphics bus and draws graphics at high speed and low cost. The apparatus employs graphics processing units connected in parallel. Each of the units is formed on a chip and has a graphics processor and a graphics memory, to provide color information and select information. The outputs of the units are selected through a tournament.

Abstract: A method and system for providing multiple typographic glyph data items to a requesting client from a font scaler sub-system. The method and system includes accepting a request from the client that describes multiple glyphs and a destination memory in which to store the glyphs. From the request, a transaction message is formed and transmitted to a scaler server using an application program interface. The scaler server then generates the multiple glyph data items from the descriptions of the multiple glyphs, and stores the glyph data items directly into the destination memory.

Abstract: In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

Abstract: The present invention provides a method and apparatus for transferring a video image, to be resized, from a host processor to an accelerator chip of a display adapter such that the storage capacity of a memory device in the chip is greatly reduced. The video data is first divided into M×M arrays of data elements. Then, the arrays are transferred one row at a time. Each row is stored before being processed by the chip. Consequently, since these rows are much shorter than the lines of frames of data elements, the storage capacity of the chip's memory device is greatly reduced.

Abstract: A simulation display system includes input deciding means for designating an external signal, a signal which is replaced by an event or an event, and an animation block for displaying the operation of problem to be subjected to simulation by animation on the basis of the signal or the event designated by the input deciding means.