Abstract: An engine fuel delivery control system includes an engine having at least one fuel injector fuel injector responsive to electronic control signals for delivering fuel to the engine cylinders and a plurality of sensor for supplying electrical sensor signals as various functions of engine operating conditions. An electronic engine control unit includes an electronic memory storing engine control parameters in a variety of look-up tables, a microprocessor-based controller for periodically addressing the memory tables and obtaining required control parameters as a function of sensor signal inputs, and circuitry for supplying control signals to the injectors as a predetermined function of the control parameters obtained from the look-up tables.

Abstract: Programmable logic cells, and arrays of those cells, having certain characteristics, including: (1) the ability to program each cell to act either as a logic element or as a logical identity element(s) between one or more inputs and one or more outputs; (2) the ability to rotate circuits by 90.degree. and to reflect circuits about horizontal and vertical axes; (3) an integrated logic and communication structure which emphasizes strictly local communications; (4) a minimal complexity of logic functions available at the cell level, making available a very fine-grained logic structure; and (5) suitability for implementation of both synchronous and asynchronous logic, including speed-independent circuits. Cells are arranged in a grid, with each cell communicating with its north, east, west and south neighbors. The cells are programmable to several states.

Abstract: A navigation apparatus in which the scale of a displayed map is automatically adjusted in dependence on parameter such as the distance between the moving object and a preselected destination.

Abstract: A design layout sequence for an application specific integrated circuit such as an ECL gate array includes a schematic capture step, which results in a logic netlist file, and a placement and routing step which results in a number of various files defining, for example bias drivers, I/O macros, and relationships between chip pads and I/O signals. The design layout sequence culminates in a physical data base file. To ensure a functional design, the designer's work is simulated after both schematic capture and placement and routing using a library containing simulation models for each type of macrocell used in the design. The gate-level netlist component of the simulation models are created automatically in a computer-implemented technique that identifies each root in the combinatorial circuit, assigns each a logical value, and traverses the tree that originates from each identified root.

Abstract: A method for producing a mask pattern for a semiconductor integrated circuit includes dividing the mask pattern data into a plurality of lower level cells and an upper level cell having wiring lines for providing connections between the lower level cells, extracting inter-cell connection information from the mask pattern data, changing the dimensions of the lower level cells by predetermined ratios to conform to a design standard, and changing the wiring lines of the upper level cell to retain the connection between the lower level cells in accordance with the inter-cell connection information extracted.

Abstract: In a system of digital chips, the time delay in all clock trees is equalized by equalizing the delay through each level of all trees. The level delays are equalized by adjusting the capacitance of terminators in each net at each level, and/or by adjusting the performance (power) of each driver at each level. Where the capacitance of a net is too low to be compensated by a driver, a capacitive terminator is selectively added to that net.

Abstract: A differential limiting force control system for controlling a slip limiting force by controlling an engagement force of a clutch assembly of a limited slip differential provided between left and right drive wheels of a vehicle includes a control unit having a basic control section for increasing the differential limiting force with increase of a vehicle speed, and an adjusting section for decreasing the differential limiting force when a steering angle is equal to or lower than a predetermined angle, or when a steering angular speed is equal to or higher than a predetermined angle.

Abstract: A system and method for routing interconnections through the layout of an integrated circuit is used in conjunction with a sliceable circuit layout specification that specifies the regions of the layout occupied by circuit components, a specification of the locations of terminals in the layout, and a netlist specifying for each terminal the set of other terminals that are to be connected to it. The regions of the circuit layout not occupied by circuit components are called routing regions. The circuit layout is sequentially sliced, defining a series of rectangular channels, each of which divides a region of the circuit layout containing two or more circuit components into two circuit regions each having at least one circuit component. For each channel, if there are one or more neighboring indented routing regions, a special channel is defined for each such indentation.

Abstract: A method and apparatus for detecting flaws in continuous web material illuminated by a light source and optically scanned to produce a digitalized electronic image of said material. The digitized image data representative of the continuous web material is stored in memory. The image data is also applied to a digital signal processor which identifies areas of the image which represent potential flawed areas of the continuous web material. A variety of spatial matched filters are employed to detect the flaws. Information concerning the locations of the potential flaws is transferred to a computer which analyzes in detail portions of the stored image in the vicinity of the identified areas. The processing performed in the computer verifies the presence of flaws in the material.

Abstract: A circuit design conversion apparatus comprises hierarchical circuit data memory, hierarchical structure analyzer, hierarchical structure data memory, conversion module register, conversion rule memory, conversion module table memory, conversion control unit, module pick-up unit, circuit design conversion unit and conversion rule remake unit. Circuit connection data which hierarchically described the connection of an LSI is input to the hierarchial circuit data memory. Hierarchical structure analyzer analyzes the circuit structure to obtain a hierarchical structure data, which in turn is stored in the hierarchical structure data memory. The name of a module, to be scan designed, is initially registered in the conversion rule memory. Considering the hierarchical structure data and the conversion rule the name of a module higher in level than the module registered in the conversion rule is registered in conversion module table memory which includes a pointer for representing a modules to be scan designed next.

Abstract: A decoding type select logic generating method includes the steps of listing on a group basis input signal names and output destination signal names contained in register transfer descriptions and control codes for commanding execution of the register transfers for each of the same input signal names and same output destination signal names, simplifying logics by replacing the control code having the hamming distance of one by a bit meaning "don't care" on the group basis, generating AND gates for the control codes and the input signal names in each of the groups having the same input signal name and combining the outputs of the AND gates, generating AND gates for the control codes in each group having the same output destination signal name and combining the outputs of the AND gates for each of the output destination signal names, and combining the outputs of the groups each having the same input signal name and the groups each having the same output destination signal name.

Abstract: A printed circuit layout system using two or more of the following sub-systems: a pattern processing subsystem, a pattern design rule check subsystem, and a pattern connectivity verification characterizes any circuit pattern by a set of rectangles, each rectangle identified by a potential number and a layer, number and coordinates, and identifies terminals by potential number, layer number, and terminal names. The system eliminates the need to perform pattern OR processing and electrical connectivity search, as required by conventional schemes. The reforming and checking processes for the layout patterns are executed by a simple high speed method, making use of the features of the layout data. The system includes efficient methods for notch elimination, design rule checking, and connectivity checking.

Abstract: A flight recorder (MPV) is contained within a two-walled chassis (11, 13), of which the walls are separated by a fire-resistant material (12). The memory means consist of hybrid circuits (H1-H8) of the EEPROM type. These are associated with a control card that may act as a fuse. The hybrid circuits (H1-H8) are mounted so as to be pressure-resistant. The flight parameters are alternating recorded on two memory cards (MC1 and MC2) and also in their hybrid circuits.

Abstract: A method and apparatus for tracking and identifying printed circuit assemblies is presented. Information about each printed circuit assembly (PCA), including the current revision level of the PCA is stored within a non-volatile random access memory (RAM) within each PCA. The stored information may be accessed by a user through a dedicated bus and hardware designed for this task. Additionally, through the dedicated bus and hardware, the user may update the information within the printed circuit assembly.

Abstract: A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.

Abstract: A wheel acceleration slip control device for a vehicle, such as an automobile, in which the degree of opening of the throttle is controlled according to the difference between a driven wheel corresponding speed or driven wheel speed and each of a first and a second threshold values which are determined with respect to a vehicle speed. Control maintains the degree of the degree of opening of the throttle when the driven wheel corresponding speed or driven wheel speed is between the first and second threshold values, whereby excessively large variations of engine torque are prevented, the engine speed can be stably increased, and the vehicle can be smoothly accelerated.

Abstract: A method of simulating the operation of a circuit utilizing voltage or current data obtained from measurements of actual samples of each of the circuit components. The actually measured voltage or current data is employed to mathematically analyze operation of the circuit. In this process, each circuit component is characterized as one or more of a voltage controlled voltage source, voltage controlled current source, current controlled voltage source and current controlled current source. After such characterization, a trial operating point is selected and values of current or voltage between actually measured data points are determined and linearized circuit equations are established with spline equations. The linearized equations are solved. The steps are repeated with a new trial operating point in accordance with a Newton-Rhapson iterative technique until the solution of the linearized equations is within a predetermined range.

Abstract: In a standard cell LSI including functional circuits formed by placing a group of cell rows consisting of standard cells selected from a group of standard cells and by routing the standard cells, a standard cell LSI layout method including the steps of comparing the routing density in routing areas located between the cell rows and bending the cell rows by shifting one or more of the standard cells in a direction of a more dispersed routing area from a more congested routing area. The cell rows are bent at a point between each high congested area of the routing area which encloses the cell rows depending on the routing density. A link cell may be provided for linking power and ground pins of the standard cells which have been shifted in position and which compose the bent cell rows. The link cell may be stored in a library in a system of composing the cell rows by storing the standard cells in a library and referring to the standard cells from the library in defining a standard cell LSI layout.

Abstract: A method of designing semiconductor integrated circuits wherein rough routes are designated after a process of design for cells layout is completed, then wirings between cells are supposed automatically on the basis of the designated rough routes, investigation of the characteristic of the wirings is executed, and after a target characteristic is attained, a wiring pattern satisfying all of required electrical and physical conditions, including layout rules, i.e. a detailed wiring pattern, is prepared.

Abstract: Controlling ignition current in the ignition control system of an internal combustion engine includes determining the amount of time it takes current in the ignition coil to reach a desired or limit value and adjusting the time of starting ignition coil charging before spark firing to be substantially equal to the amount of time it takes ignition coil charging current to reach the desired or limit current value.